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INTEGRATED CIRCUITS
DATA SHEET
SAA7196 Digital video decoder, Scaler and Clock generator circuit (DESCPro)
Product specification File under Integrated Circuits, IC22 1996 Nov 04
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
CONTENTS 1 2 3 4 5 6 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.4 7.4.1 7.4.2 7.4.3 7.4.3.1 7.4.4 7.4.5 7.4.5.1 7.4.5.2 7.4.5.3 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 7.4.10.1 7.4.10.2 7.4.10.3 7.4.10.4 7.4.11 7.4.12 7.5 8 8.1 8.2 8.3 8.4 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Decoder part Chrominance processor Luminance processor Synchronization Expansion port (see Fig.2) Monitor controls BCS (see Fig.2) Brightness and contrast controls; see Tables 1 and 2 Saturation control; see Table 3 RTCO output pin 44 (see Fig.11) RTS1 and RTS0 outputs (pins 34 and 35) Scaler part Decimation filters Vertical processing (VPU_Y) RGB matrix Anti-gamma ROM tables Chrominance signal keyer Scale control and vertical regions Vertical bypass region Vertical scaling region Vertical regions (see Fig.12) Output data representation and levels Output FIFO register and VRAM port VRAM port transfer procedures Data burst transfer mode Transparent data transfer mode Interlaced processing (OF bits, subaddress 20) INCADR timing Monochrome format (see Table 10) VRAM port specifications Field processing Operation cycle Power-on reset PROGRAMMING MODEL I2C-bus format I2C-bus status information Decoder part Scaler part 9 10 11 12 12.1 13 14 14.1 14.2 14.3 14.4 15 16 17 LIMITING VALUES CHARACTERISTICS PROCESSING DELAYS
SAA7196
APPLICATION INFORMATION Programming example PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1996 Nov 04
2
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
1 FEATURES * I2C-bus control * Only one crystal of 26.8 MHz required * Clock generator on chip. 2 GENERAL DESCRIPTION
SAA7196
* Digital 8-bit luminance input [video (Y) or CVBS] * Digital 8-bit chrominance input [CVBS or C from CVBS, Y/C, S-Video (S-VHS or Hi8)] * Luminance and chrominance signal processing for main standards PAL, NTSC and SECAM * Horizontal and vertical sync detection for all standards * User programmable luminance peaking for aperture correction * Compatible with memory-based features (line-locked clock, square pixel) * Cross colour reduction by chrominance comb-filtering for NTSC or special cross-colour cancellation for SECAM * UV signal delay lines for PAL to correct chrominance phase errors * Square-pixel format with 768/640 active samples per line * The bidirectional expansion port (YUV-bus) supports data rates of 780 x fH (NTSC) and 944 x fH (PAL, SECAM) in 4 : 2 : 2 format * Brightness, contrast, hue and saturation controls for scaled outputs * Down-scaling of video windows with 1023 active samples per line and 1023 active lines per frame to randomly sized windows * 2D data processing for improved signal quality of scaled luminance data, especially for compression applications * Chroma key (-generation) * YUV to RGB conversation including anti-gamma ROM tables for RGB * 16-word output FIFO (32-bit words) * Output configurable for 32-, 24- and 16-bit video data bus * Scaled 16-bit 4 : 2 : 2 YUV output * Scaled 15-bit RGB (5-5-5+) and 24-bit (8-8-8+) output * Scaled 8-bit monochrome output * Line increment, field sequence (odd/even, interlace/non-interlaced) and vertical reset control for easy memory interfacing * Output of discontinuous data bursts of scaled video data or continuous data output with corresponding qualifier signals * Real-time status information
The CMOS circuit SAA7196, digital video decoder, scaler and clock generator (DESCPro), is a highly integrated circuit for DeskTop Video applications. It combines the functions of a digital multistandard decoder (SAA7191B), a digital video scaler (SAA7186) and a clock generator (SAA7197). The decoder is based on the principle of line-locked clock decoding. It runs at square-pixel frequencies to achieve correct aspect ratio. Monitor controls are provided to ensure best display. Four data ports are supported: * Port CVBS7 to CVBS0 of input interface; used in Y/C mode (see Fig.1) to decode digitized luminance and chrominance signals (digitized in two external ADCs). In normal mode, only this input port is used and only one ADC is necessary (see Fig.4) * Port CHR7 to CHR0 of input interface; used in Y/C mode (see Fig.1) to decode digitized luminance and chrominance signals (digitized in two external ADCs) * 32-bit VRAM output port; interface to the video memory. It outputs the down-scaled video data; different formats and operation modes are supported by this circuit * 16-bit expansion port; this is a bidirectional port. In general, it establishes the digital YUV as known from the SAA71x1 family of digital decoders. In addition, the expansion port is configurable to send data from the decoder unit or to accept external data for input into the scaler. In input mode the clock rate and/or the sync signals may be delivered by the external data source. Decoder and scaler units can run at different clock rates. The decoder processing always operates with a Line Locked Clock (LLC). This clock is derived from the CVBS signal and is suited best for memory based video processing; the LLC clock is always present. The scaler clock may be driven by the LLC clock or by an external clock depending on the configuration of the expansion port.
1996 Nov 04
3
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
The circuit is I2C-bus controlled. The I2C-bus interface is clocked by LLC to ensure proper control. The I2C-bus control is identical to that of the SAA7194. It is divided into two sections: * Subaddress 00H to 1FH for the decoder part (Tables 16 and 17) * Subaddress 20H to 3FH for the scaler part (Tables 29 and 30). 3 QUICK REFERENCE DATA Measured over full voltage and temperature ranges. SYMBOL VDD IDD(tot) VI VO fBCK Tamb 4 supply voltage total supply current data input level data output level input clock frequency operating ambient temperature - 0 PARAMETER - MIN. 4.5 5 180 TYP.
SAA7196
The programming of the subaddresses for the scaler part becomes effective at the first Vertical Sync (VS) pulse after a transmission.
MAX. 5.5 280 V
UNIT mA
TTL-compatible TTL-compatible - - 32 70 MHz C
ORDERING INFORMATION PACKAGE
TYPE NUMBER NAME SAA7196H QFP120 DESCRIPTION plastic quad flat package; 120 leads (lead length 1.95 mm); body 28 x 28 x 3.4 mm; high stand-of height VERSION SOT349-1
1996 Nov 04
4
5
Product specification
SAA7196
Fig.1 Block diagram of decoder part (continued in Fig.2).
handbook, full pagewidth
1996 Nov 04
+5 V VDDD1 to VDDD7 RTCO 44 76, 105 15 37 CGCE CTST 14, 31, 45, 61, 77, 91, 106 16, 30, 47, 60, 75, 104, 120 VSSD1 to VSSD7
Philips Semiconductors
BLOCK DIAGRAM
internally connected +5 V
RES CGC
36
SAA7196 DECODER PART
HREF A B C CHROMINANCE PROCESSOR 8 UV7 to UV0 8 Y7 to Y0
8
CHR7 to CHR0
13 to 6
INPUT INTERFACE LUMINANCE PROCESSOR VDD VSS clock clock A 2 HS, VS F status SYNC PLIN
8
D E
CVBS7 to CVBS0
24 to 17
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
5
I2C-BUS CONTROL SYNCHRONIZATION CLOCK A GENERATOR 5 26 28 34 25 35 29 27 +5 V HSY HCL control and status to and from scaler part LFCO RTS1 RTS0 VSSA VDDA XTALI XTAL LLC 1 2 40
GPSW1
33
to scaler part
GPSW2
32
PORT AND STATUS REGISTER
SDA
3
CREF
G LLC
SCL
4
H
38
I2CSA
CREF
MHA381
Product specification
SAA7196
Fig.2 Block diagram of brightness, contrast, saturation controls and scaler part (continued from Fig.1).
handbook, full pagewidth
1996 Nov 04
VOEN VCLK 56 53 43 BTST
Philips Semiconductors
VERTICAL FILTER
8 8 8 Y ARITHMETIC V U INTERPOLATOR V 15 CHROMA KEYER 54 55 U FOLLOWED BY ANTI-GAMMA ROMs LUMINANCE DECIMATION FILTER LINE MEMORY (8 x 384) Y
RGB MATRIX VRO31 to VRO0 32-bit VRAM port output RGB or YUV
57 to 59 62 to 74 78 to 90 OUTPUT FORMATTER 92 to 94
BRIGHTNESS CONTRAST AND SATURATION CONTROLS (BCS) UV OUTPUT FIFO REGISTER CHROMA DECIMATION FILTER HFL
INCADR
D
VDD VS
HREF
YUV15 to YUV0 SCALE CONTROL
46 48 49 50 51 52
VMUX SODD SVS SHREF PXQ LNQ
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
6
CREFINB BUS INTERFACE LLCINB CLOCK B GENERATOR clock B to scaler and brightness, contrast saturation controls 118 AP DIR HREF expansion port HS LLCB VS CREFB LLC2 95 116 117 39 41 115 42
E
VSS
A
HREF
B
UV7 to UV0 8
SAA7196 SCALER PART
from decoder part
C
Y7 to Y0
8
F
HS, VS
G
CREF
H
LLC
YUV15 to YUV0
119 SP
MHA382
96 to 103 107 to 114
input/output
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
6 PINNING SYMBOL XTAL XTALI SDA SCL I2CSA CHR0 CHR1 CHR2 CHR3 CHR4 CHR5 CHR6 CHR7 VDDD1 CTST VSSD1 CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 HSY HCL VDDA LFCO VSSA VSSD2 VDDD2 GPSW2 GPSW1 RTS1 RTS0 RES CGCE CREF PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 STATUS O I I/O I I I I I I I I I I - - - I I I I I I I I O O - O - - - O O O O O I O DESCRIPTION
SAA7196
26.8 MHz crystal oscillator output, not used if TTL clock signal is used 26.8 MHz crystal oscillator input or external clock input (TTL, square wave) I2C-bus data line I2C-bus clock line I2C-bus set address digital chrominance input signal (bit 0) digital chrominance input signal (bit 1) digital chrominance input signal (bit 2) digital chrominance input signal (bit 3) digital chrominance input signal (bit 4) digital chrominance input signal (bit 5) digital chrominance input signal (bit 6) digital chrominance input signal (bit 7) +5 V digital supply voltage 1 connected to ground (clock test pin) digital ground 1 (0 V) digital CVBS input signal (bit 0) digital CVBS input signal (bit 1) digital CVBS input signal (bit 2) digital CVBS input signal (bit 3) digital CVBS input signal (bit 4) digital CVBS input signal (bit 5) digital CVBS input signal (bit 6) digital CVBS input signal (bit 7) horizontal sync indicator output (programmable) horizontal clamping pulse output (programmable) +5 V analog supply voltage line frequency control output signal to CGC (multiple of present line frequency) analog ground (0 V) digital ground 2 (0 V) +5 V digital supply voltage 2 general purpose output 2 (controllable via I2C-bus) general purpose output 1 (controllable via I2C-bus) real time status output 1; controlled by bit RTSE real time status output 0; controlled by bit RTSE reset output, active LOW enable input for internal CGC (connected to +5 V) clock qualifier output (test only)
1996 Nov 04
7
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SYMBOL CREFB LLC PIN 39 40 STATUS I/O O DESCRIPTION
SAA7196
clock reference qualifier input/output (HIGH indicates valid data on expansion port) line-locked video system clock output, for front-end (ADCs) only; frequency: 1888 x fH for 50 Hz/625 lines per field systems and 1560 x fH for 60 Hz/525 lines per field systems line-locked clock signal input/output, maximum 32 MHz (twice of pixel rate in 4 : 2 : 2); frequency: 1888 x fH for 50 Hz/625 lines per field systems and 1560 x fH for 60 Hz/525 lines per field systems; or variable input clock up to 32 MHz in input mode line-locked clock signal output (pixel clock) connected to ground; BTST = HIGH sets all outputs (except pins 1, 28, 38, 40 and 42) to high-impedance state (testing) real time control output +5 V digital supply voltage 3 VRAM output multiplexing, control input for the 32- to 16-bit multiplexer (see Table 7) digital ground 3 (0 V) odd/even field sequence reference output related to the scaler output (test only) vertical sync signal related to the scaler output (test only) delayed HREF signal related to the scaler output (test only) pixel qualifier output signal to mark active pixels of a qualified line (polarity: bit QPP; test only) line qualifier output signal to mark active video phase (polarity: bit QPP; test only) enable input of VRAM output FIFO half-full flag output signal line increment/vertical reset control output clock input signal of FIFO output 32-bit digital VRAM output port (bit 31) 32-bit digital VRAM output port (bit 30) 32-bit digital VRAM output port (bit 29) digital ground 4 (0 V) +5 V digital supply voltage 4 32-bit VRAM output port (bit 28) 32-bit VRAM output port (bit 27) 32-bit VRAM output port (bit 26) 32-bit VRAM output port (bit 25) 32-bit VRAM output port (bit 24) 32-bit VRAM output port (bit 23) 32-bit VRAM output port (bit 22) 32-bit VRAM output port (bit 21) 32-bit VRAM output port (bit 20) 8
LLCB
41
I/O
LLC2 BTST RTCO VDDD3 VMUX VSSD3 SODD SVS SHREF PXQ LNQ VOE HFL INCADR VCLK VRO31 VRO30 VRO29 VSSD4 VDDD4 VRO28 VRO27 VRO26 VRO25 VRO24 VRO23 VRO22 VRO21 VRO20 1996 Nov 04
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
O I O - I - O O O O O I O O I O O O - - O O O O O O O O O
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SYMBOL VRO19 VRO18 VRO17 VRO16 VSSD5 i.c. VDDD5 VRO15 VRO14 VRO13 VRO12 VRO11 VRO10 VRO9 VRO8 VRO7 VRO6 VRO5 VRO4 VRO3 VDDD6 VRO2 VRO1 VRO0 DIR YUV15 YUV14 YUV13 YUV12 YUV11 YUV10 YUV9 YUV8 VSSD6 i.c. VDDD7 YUV7 YUV6 YUV5 YUV4 YUV3 1996 Nov 04 PIN 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 STATUS O O O O - - - O O O O O O O O O O O O O - O O O I I/O I/O I/O I/O I/O I/O I/O I/O - - - I/O I/O I/O I/O I/O DESCRIPTION 32-bit VRAM output port (bit 19) 32-bit VRAM output port (bit 18) 32-bit VRAM output port (bit 17) 32-bit VRAM output port (bit 16) digital ground 5 (0 V) internally connected +5 V digital supply voltage 5 32-bit VRAM output port (bit 15) 32-bit VRAM output port (bit 14) 32-bit VRAM output port (bit 13) 32-bit VRAM output port (bit 12) 32-bit VRAM output port (bit 11) 32-bit VRAM output port (bit 10) 32-bit VRAM output port (bit 9) 32-bit VRAM output port (bit 8) 32-bit VRAM output port (bit 7) 32-bit VRAM output port (bit 6) 32-bit VRAM output port (bit 5) 32-bit VRAM output port (bit 4) 32-bit VRAM output port (bit 3) +5 V digital supply voltage 6 32-bit VRAM output port (bit 2) 32-bit VRAM output port (bit 1) 32-bit VRAM output port (bit 0) direction control of expansion bus
SAA7196
digital 16-bit video input/output signal (bit 15); luminance (Y) digital 16-bit video input/output signal (bit 14); luminance (Y) digital 16-bit video input/output signal (bit 13); luminance (Y) digital 16-bit video input/output signal (bit 12); luminance (Y) digital 16-bit video input/output signal (bit 11); luminance (Y) digital 16-bit video input/output signal (bit 10); luminance (Y) digital 16-bit video input/output signal (bit 9); luminance (Y) digital 16-bit video input/output signal (bit 8); luminance (Y) digital ground 6 (0 V) internally connected +5 V digital supply voltage 7 digital 16-bit video input/output signal (bit 7); colour difference signals (UV) digital 16-bit video input/output signal (bit 6); colour difference signals (UV) digital 16-bit video input/output signal (bit 5); colour difference signals (UV) digital 16-bit video input/output signal (bit 4); colour difference signals (UV) digital 16-bit video input/output signal (bit 3); colour difference signals (UV) 9
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SYMBOL YUV2 YUV1 YUV0 HREF VS HS AP SP VSSD7 PIN 112 113 114 115 116 117 118 119 120 STATUS I/O I/O I/O I/O I/O O I I - DESCRIPTION
SAA7196
digital 16-bit video input/output signal (bit 2); colour difference signals (UV) digital 16-bit video input/output signal (bit 1); colour difference signals (UV) digital 16-bit video input/output signal (bit 0); colour difference signals (UV) horizontal reference signal vertical sync input/output signal with respect to the YUV input signal horizontal sync signal, programmable connected to ground (action pin for testing) connected to ground (shift pin for testing) digital ground 7 (0 V)
1996 Nov 04
10
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
106 VDDD7 105 i.c. 104 VSSD6
101 YUV10
100 YUV11
99 YUV12
98 YUV13
97 YUV14
96 YUV15
94 VRO0
115 HREF
114 YUV0
113 YUV1
112 YUV2
111 YUV3
110 YUV4
109 YUV5
108 YUV6
107 YUV7
103 YUV8
102 YUV9
117 HS
118 AP
XTAL XTALI SDA SCL I2CSA CHR0 CHR1 CHR2 CHR3
1 2 3 4 5 6 7 8 9
116 VS
93 VRO1
handbook, full pagewidth
120 VSSD7 119 SP
92 VRO2 91 VDDD6 90 VRO3 89 VRO4 88 VRO5 87 VRO6 86 VRO7 85 VRO8 84 VRO9 83 VRO10 82 VRO11 81 VRO12 80 VRO13 79 VRO14 78 VRO15 77 VDDD5 76 i.c. 75 VSSD5 74 VRO16 73 VRO17 72 VRO18 71 VRO19 70 VRO20 69 VRO21 68 VRO22 67 VRO23 66 VRO24 65 VRO25 64 VRO26 63 VRO27 62 VRO28 61 VDDD4 VRO29 59 VSSD4 60
MHA379
CHR4 10 CHR5 11 CHR6 12 CHR7 13 VDDD1 14 CTST 15 VSSD1 16 CVBS0 17 CVBS1 18 CVBS2 19 CVBS3 20 CVBS4 21 CVBS5 22 CVBS6 23 CVBS7 24 HSY 25 HCL 26 VDDA 27 LFCO 28 VSSA 29 VSSD2 30 VDDD2 31 GPSW2 32 GPSW1 33 RTS1 34 RTS0 35 RES 36 CGCE 37 CREF 38 CREFB 39 LLC 40 LLCB 41 LLC2 42 BTST 43 RTCO 44 VDDD3 45 VMUX 46 VSSD3 47 SODD 48 SVS 49 SHREF 50 PXQ 51 LNQ 52 VOE 53 HFL 54 INCADR 55 VCLK 56 VRO31 57 VRO30 58
SAA7196
Fig.3 Pin configuration.
1996 Nov 04
11
95 DIR
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
7 7.1 FUNCTIONAL DESCRIPTION Decoder part
SAA7196
PAL, NTSC and SECAM standard colour signals based on line-locked clock are decoded (see Fig.27). In Y/C mode, digitized luminance CVBS7 to CVBS0 and chrominance CHR7 to CHR0 signals (digitized in two external ADCs) are input. In normal mode only CVBS7 to CVBS0 is used. The data rate is 29.5 MHz (50 MHz systems) or 24.54 MHz (60 MHz systems). 7.1.1 CHROMINANCE PROCESSOR
centre frequency of 3.58 MHz (NTSC) or 4.4 MHz (PAL, SECAM) to eliminate most of the colour carrier components. The chrominance trap is bypassed for S-VHS signals. The high frequency components in the luminance signal are `peaked' using a band-pass filter and a coring stage. The `peaked' (high frequent) component is added to the `unpeaked' signal part for sharpness improvement and output via variable delay to the expansion bus. 7.1.3 SYNCHRONIZATION
The input signal passes the input interface and the chrominance band-pass filter to eliminate DC components and is finally fed to the multiplicative inputs of a quadrature demodulator, where two subcarrier signals (0 and 90 phase-shifted) from a local digital oscillator (DTO1) are applied. The frequency is dependent on the present colour standard. The signals are low-pass filtered and amplified in a gain-controlled amplifier. A final low-pass stage provides a correct bandwidth performance. PAL signals are comb-filtered to eliminate crosstalk between the chrominance channels according to PAL standard requirements. NTSC signals are comb-filtered to eliminate crosstalk from luminance to chrominance for vertical structures. SECAM signals are fed through a cloche filter, a phase demodulator and a differentiator to achieve proportionality to the instantaneous frequency. The signals are de-multiplexed in the SECAM recombination stage after passing a de-emphasis stage to provide the two serially transmitted colour difference signals. The PLL for quadrature demodulation is closed via the cloche filter (to improve noise performance), a phase demodulator, a burst gate accumulator, a loop filter PI1 and a discrete time oscillator DTO1. The gain control loop is closed via the cloche filter, amplitude detector, a burst gate accumulator and a loop filter PI2. The sequence processor switches signals according to standards. 7.1.2 LUMINANCE PROCESSOR
The sync input signal is reduced in bandwidth to 1 MHz before it is sliced and separated from the luminance signal. The sync pulses are compared in a detector with the divided clock signal of a counter. The resulting output signal is fed to a loop filter that accumulates all the phase deviations. Thereby, a discrete time oscillator DTO2 is driven generating the line frequency control signal LFCO. An external PLL generates the line-locked clock LLC from the signal LFCO. A noise-limited vertical deflection pulse is generated for vertical processing that also inserts artificial pulses if vertical input pulses are missing. 50/60 Hz as well as odd/even field is automatically detected by the identification stage. 7.2 Expansion port
The expansion port is a bidirectional interface for digital video signals YUV15 to YUV0 in 4 : 2 : 2 format (see Table 5). External video signals can be inserted to the scaler or decoded video signals of the decoder part can be output. The data direction is controlled by pin 95 (DIR = HIGH: data from external; see Table 4). YUV15 to YUV0, HREF, VS, LLCB and CREFB pins are inputs when bits OECL, OEHV, OEYC of subaddress 0E are set to `0'. Different modes are provided (for timing see Figs 6 to 8): * Mode 0: all bidirectional terminals are outputs. The signal of the decoder part (internal YUV15 to YUV0) is switched to be scaled. * Mode 1: external YUV15 to YUV0 is input to the scaler. LLCB/CREFB clock system and HREF/VS from the SAA7196 are used to control the external source. It is possible to switch between mode 0 and mode 1 by means of DIR input (see Fig.5). * Mode 2: External YUV15 to YUV0 is input to the scaler. LLCB/ CREFB clock system and HREF/VS from external are used.
The data rate of the input signal is reduced to LLC2 frequency by a sample rate converter in the input interface. The high frequency components are emphasized in a prefilter to compensate for losses in the succeeding chrominance trap. The chrominance trap is adjusted to a
1996 Nov 04
12
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
* Mode 3: YUV15 to YUV0 and HREF/VS terminals are inputs. External YUV15 to YUV0 is input to the scaler with HREF/VS reference from external. LLCB/CREFB clock system of the SAA7196 is used.
SAA7196
pixel wise switching of the scaler source is possible because the internal clock and sync sources are used.
handbook, full pagewidth
+127 reserved +106 +95 100% white (60 Hz mode) 100% white (50 Hz mode)
digital signal value
luminance 60 Hz mode luminance 50 Hz mode 0 chrominance 50 Hz mode chrominance 60 Hz mode
-52 -64 blanking level
black (60 Hz mode) = black (50 Hz mode)
-91 -103 -128 clipped -132
MHA380
sync
All levels are related to EBU colour bar. Values in decimal at 100% luminance and 75% chrominance amplitude.
Fig.4 CVBS7 to CVBS0 input signal ranges.
1996 Nov 04
13
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
7.3 7.3.1 Monitor controls BCS BRIGHTNESS AND CONTRAST CONTROLS 7.3.2 SATURATION CONTROL
SAA7196
The luminance signal can be controlled via I2C-bus (see Table 16) by the bits BRIG7 to BRIG0 and CONT6 to CONT0. Table 1 Brightness control VALUE minimum offset CCIR level maximum offset Contrast control VALUE luminance off CCIR level 1.9999 amplitude
The chrominance signal can be controlled via I2C-bus (see Table 16) by the bits SAT6 to SAT0 and HUE7 to HUE0. Table 3 Saturation control VALUE colour off CCIR level 1.9999 amplitude
SATURATION CONTROL 00H 40H 7FH
BRIGHTNESS CONTROL 00H 80H FFH Table 2
Clipping: all resulting output values are clipped to minimum (equals 1) and maximum (equals 254).
CONTRAST CONTROL 00H 40H 7FH
Table 4 MODE
Operation modes; notes 1 to 3 I2C BIT OEYC OEHV 1 1 0 0 OECL 1 1 0 1 DIR PIN 95 LOW HIGH HIGH HIGH YUV O I I I HREF O O I I INPUT SOURCE VS O O I I LLCB O O I O CREFB O O I O
0 1 2 3 Notes
1 X X X
1. X = don't care. 2. I = input to monitor control/scaler. 3. O = output from decoder.
1996 Nov 04
14
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
Table 5 YUV-bus format on expansion port; note 1
SAA7196
PIN n YUV15 YUV14 YUV13 YUV12 YUV11 YUV10 YUV9 YUV8 YUV7 YUV6 YUV5 YUV4 YUV3 YUV2 YUV1 YUV0 Note Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0
SIGNALS ON EXPANSION PORT (PIXEL BYTE SEQUENCE ON PINS) PIXEL ORDER n+1 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 n+2 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n+3 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 n+4 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0
1. e = even pixel number; o = odd pixel number.
1996 Nov 04
15
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, full pagewidth
LLCB
tto 3-state CREFB
tfrom 3-state
HREF tSU DIR tPZ tOH UVdec (from decoder) UVext (from external port) U0(dec) UV to scaler
MHA383
tHD
U0(dec)
V0(dec) U2(ext) V2(ext)
U4(dec)
V4(dec)
V0(dec)
U2(ext)
V2(ext)
U4(dec)
V4(dec)
tfrom 3-state(min) = 1.5LLC + tPZ(min) tfrom 3-state > tto 3-state tto 3-state(max) = 1.5LLC + tPZ(max)
Fig.5 Real-time switching between mode 0 and mode 1 (internal/external YUV15 to YUV0).
1996 Nov 04
16
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, full pagewidth
625
1
2
3
4
5
6
7
8
9
input CVBS
HREF 540 x 2/LLC VS 1 x 2/LLC ODD (RTSO)
MHA384
a. 1st field.
handbook, full pagewidth
313
314
315
316
317
318
319
320
321
input CVBS
HREF 68 x 2/LLC VS 1 x 2/LLC ODD (RTSO)
MHA385
b. 2nd field
Fig.6 VS and ODD timing on expansion port (50 Hz).
1996 Nov 04
17
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, full pagewidth
525
1
2
3
4
5
6
7
8
9
input CVBS
HREF 448 x 2/LLC VS 1 x 2/LLC ODD (RTSO)
MHA386
a. 1st field.
handbook, full pagewidth
263
264
265
266
267
268
269
270
271
input CVBS
HREF 58 x 2/LLC VS 1 x 2/LLC ODD (RTSO)
MHA387
b. 2nd field.
Fig.7 VS and ODD timing on expansion port (60 Hz).
1996 Nov 04
18
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, full pagewidth
62 x 2/LLC
0 burst
CVBS
HSY +191 HSY (1) programming range (step size: 2/LLC) HCL +127 HCL (1) programming range (step size: 2/LLC) -128 0 -64
0 216 LLC 10 x 2/LLC
processing delay CVBS - YUV at YDEL = 000b Y-output
HREF (50 Hz) 768 x 2/LLC PLIN (RTS1) (50 Hz only) 36 x 2/LLC HS (50 Hz) HS (50 Hz) (2) programming range (step size: 8/LLC) +117 64 x 2/LLC 0 36 x 2/LLC HREF (60 Hz) 640 x 2/LLC HS (60 Hz) HS (60 Hz) (2) programming range (step size: 8/LLC) +97 64 x 2/LLC 0 -97
MHA388
176 x 2/LLC
2 x 2/LLC
104 x 2/LLC
-118
140 x 2/LLC
Fig.8 Horizontal sync timing at HRMV = 0 and HRFS = 0 (signals HSY, HCL, HREF, PLIN and HS; 50 and 60 Hz).
1996 Nov 04
19
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
andbook, full pagewidth LLCB
CREFB
HREF
start of active line 0 U0 1 V0 2 U2 3 V2 4 U4 5 V4 6 U6 7 V6
Byte numbers for pixels: Y signal 50 Hz U and V signal
Y signal 60 Hz U and V signal
0 U0
1 V0
2 U2
3 V2
4 U4
5 V4
6 U6
7 V6
LLCB
CREFB
HREF end of active line Byte numbers for pixels: Y signal 50 Hz U and V signal 762 U762 763 V762 764 U764 765 V764 766 U766 767 V766
Y signal 60 Hz U and V signal
634 U634
635 V634
636 U636
637 V636
638 U638
639 V638
MHA389
Fig.9 Horizontal and data multiplex timing on expansion port.
1996 Nov 04
20
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, full pagewidth digital
signal value +254 +235 white 100%
digital signal value +254 +240 +212 blue 100% blue 75%
digital signal value +254 +240 +212 red 100% red 75%
+128 luminance levels
+128 U-component levels
+128 V-component levels
+44 +16 1 black +16 1
yellow 75% yellow 100%
+44 +16 1
cyan 75% cyan 100%
MHA390
a. Y signal range.
b. U signal range (B - Y).
c. V signal range (R - Y).
Fig.10 Input and output signal levels on expansion port.
7.3.3
RTCO OUTPUT PIN 44
7.3.4
RTS1 AND RTS0 OUTPUTS (PINS 34 AND 35)
This real-time control and status output signal contains serial information about actual system clock, subcarrier frequency and PAL/SECAM sequence (see Fig.11). The signal can be used for various applications in external circuits, e.g. in a digital encoder to achieve `clean' encoding.
These outputs can be configured in two modes dependent on bit RTSE (subaddress 0D): * RTSE = 0: the output RTS0 contains the odd/even field identification bit (HIGH equals odd); output RTS1 contains the inverted PAL/SECAM sequence bit [HIGH equals non-inverted (R - Y)-line/DB-line] * RTSE = 1: the output RTS0 contains the horizontal lock bit (HIGH equals PLL locked); output RTS1 contains the vertical detection bit (HIGH equals vertical sync detected).
1996 Nov 04
21
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, full pagewidth
H/L transition (counter start) 128 clock cycles
HPLL increment bits 13 to 0 13
4 bits reserve FSCPLL increment bits 22 to 0 0 22 20 15 10 5
3 bits sequence reserve bit (1) reserved (2) 10
RTCO 0 4 8 14 19 time slot (LLC/4) 63 valid not valid 67
MHA391
(1) Sequence bit: SECAM: 0 equals DB-line; 1 equals DR-line. PAL: 0 equals (R - Y) line normal; 1 equals (R - Y) line inverted. NTSC: 0 (no change). (2) Reserve bits: 276 for 50 Hz systems; 188 for 60 Hz systems.
Fig.11 RTCO timing.
7.4
Scaler part
The scaler part receives YUV15 to YUV0 input data in 4 : 2 : 2 format. The video data from the BCS control are processed in horizontal direction in two separate decimation filters. The luminance component is also processed in vertical direction (VPU_Y). Chrominance data are interpolated to a 4 : 4 : 4 format; a chroma keying bit is generated. The 4 : 4 : 4 YUV data are then converted from the YUV to the RGB domain in a digital matrix. ROM tables in the RGB data path can be used for anti-gamma correction of gamma-corrected input signals. Uncorrected RGB and YUV signals can be bypassed.
A scale control unit generates reference and gate signals for scaling of the processed video data. After data formatting to the various VRAM port formats, the scaled video data are buffered in the 16 word 32-bit output FIFO register. The scaling is performed by pixel and line dropping at the FIFO input. The FIFO output is directly connected to the VRAM output bus VRO31 to VRO0. Specific reference signals support an easy memory interfacing.
1996 Nov 04
22
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
7.4.1 DECIMATION FILTERS 7.4.3 RGB MATRIX
SAA7196
The decimation filters perform accurate horizontal filtering of the input data stream. The signal bandwidth is matched in front of the pixel decimation stage, thus disturbing artifacts, caused by the pixel dropping, are reduced. The signal bandwidth can be reduced in steps of (see Figs 29 and 30): 2-tap filter = -6 dB at 0.325 pixel rate 3-tap filter = -6 dB at 0.25 pixel rate 4-tap filter = -6 dB at 0.21 pixel rate 5-tap filter = -6 dB at 0.125 pixel rate 9-tap filter = -6 dB at 0.075 pixel rate. The different characteristics are chosen independently by I2C-bus control bits HF2 to HF0 when AFS = 0 (subaddress 28). In the adaptive mode with AFS = 1, the filter characteristics are chosen dependent on the defined sizing parameters (see Table 6). 7.4.2 VERTICAL PROCESSING (VPU_Y)
Y data and UV data are converted after interpolation into RGB data according to CCIR601 recommendation. Data is bypassed in 16-bit YUV formats or monochrome modes. The matrix equations are these considering the digital quantization: R = Y + 1.375 V G = Y - 0.703125 V - 0.34375 U B = Y + 1.734375 U.
7.4.3.1
Anti-gamma ROM tables
ROM tables are implemented at the matrix output to provide anti-gamma correction of the RGB data. A curve for a gamma of 1.4 is implemented. The tables can be used (bit RTB = 0, subaddress 20) to compensate gamma correction for linear data representation of RGB output data. 7.4.4 CHROMINANCE SIGNAL KEYER
Luminance data is fed to a vertical filter consisting of a 384 x 8-bit RAM and an arithmetic block (see Fig.2). Subsampled and interpolation operations are applied. The luminance data is processed in vertical direction to preserve the video information for small scaling factors and to reduce artifacts caused by the dropping. The available modes respectively transfer functions are selectable by bits VP1 and VP0 (subaddress 28). Adaptive modes, controlled by AFS and AFG bits (subaddresses 28 and 30) are also available (see Table 6). Table 6 Adaptive filter selection (AFS = 1) FILTER FUNCTION(1) horizontal bypassed filter 1 filter 6 filter 3 filter 4 vertical bypassed filter 1 filter 2
The keyer generates an alpha signal to achieve a 5-5-5+ RGB alpha output signal. Therefore, the processed UV data amplitudes are compared with thresholds set via I2C-bus (subaddresses `2C to 2F'). A logic `1' signal is generated if the amplitude is inside the specified amplitude range, otherwise a logic `0' is generated. Keying can be switched off by setting the lower limit higher than the upper limit (`2C or 2E' and `2D or 2F'). 7.4.5 SCALE CONTROL AND VERTICAL REGIONS
SCALING RATIO XD/XS 1 14/15 11/15 7/15 3/15 YD/YS 1 13/15 4/15 Note 1. See Chapter 8. 1996 Nov 04
The scale control block SC includes address/sequence counters to define the current position in the input field and to address the internal VPU memories. To perform scaling, XD of XS pixel selection in horizontal direction and YD of YS line selection in vertical direction are applied. The pixel and line dropping are controlled at the input of the FIFO register. The scaling ratio in horizontal and vertical direction is estimated to control the decimation filter function and the vertical data processing in the adaptive mode (AFS and AFG bits). The input field can be divided into two vertical regions - the bypass region and the scaling region, which are defined via I2C-bus by the parameters VS, VC, YO and YS.
23
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
7.4.5.1 Vertical bypass region
I2C
SAA7196
Data are not scaled and independent of bits FS1 and FS0; the output format is always 8-bit gray scale (monochrome). The SAA7196 outputs all active pixels of a line, defined by the HREF input signal if the vertical bypass region is active. This can be used, for example, to store video text information in the field memory. The start line of the bypass region is defined by the I2C bits VS; the number of lines to be bypassed is defined by VC.
shorter than XS, processing is aborted when the falling edge of HREF is detected. In this case the output line will have less than XD samples.
7.4.5.3
Vertical regions (see Fig.12)
* The two regions can be programmed via I2C-bus, whereby regions should not overlap (active region overrides the bypass region) * The start of a normal active picture depends on video standard and has to be programmed to the correct value * The offsets XO and YO have to be set according to the internal processing delays to ensure the complete number of destination pixels and lines (refer to Table 30) * The scaling parameters can be used to perform a panning function over the video frame/field.
7.4.5.2
Vertical scaling region
Data is scaled with start at line YO and the output format is selected when FS1 and FS0 are valid. This is the `normal operation' area. The input/output screen dimensions in horizontal and vertical direction are defined by the parameters XO, XS and XD for horizontal and YO, YS and YD for vertical. The circuit processes XS samples of a line. Remaining pixels are ignored if a line is longer than XS. If a line is
handbook, full pagewidth
vertical sync vertical blanking first valid line VS vertical bypass start bypass region vertical bypass count equals VS YO
scaling region start scaling region scaling region count equals YS Y-size source
MHA392
Fig.12 Vertical regions.
1996 Nov 04
24
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
7.4.6 OUTPUT DATA REPRESENTATION AND LEVELS 7.4.8
SAA7196
VRAM PORT TRANSFER PROCEDURES
Output data representation of the YUV data can be modified by bit MCT (subaddress 30). The DC gain is 1 for YUV input data. The corresponding RGB levels are defined by the matrix equations; they are limited to the range of 1 to 254 in the 8-bit domain according to CCIR 601. In the event the YUV or monochrome luminance output formats are selected and bit LLV = 1, the luminance levels can be limited to: * 16 (239) = black * 235 (20) = white * (...) = gray scale luminance levels. For the 5-bit RGB formats a truncation from 8-bit to 5-bit word width is implemented. Fill values are inserted dependent on long word position and destination size (see Section 7.4.9): * `1' for 24-bit RGB, Y and two's complement UV * `128' for UV (straight binary) * `254' in 8-bit gray scale format. 7.4.7 OUTPUT FIFO REGISTER AND VRAM PORT
Data transfer on the VRAM port can be done asynchronously controlled by outputs HFL, INCADR and input VCLK (data burst transfer with bit TTR = 0). Data transfer on the VRAM port can be done synchronously controlled by output reference signals on outputs VRO7 to VRO0 and a continuous VCLK of clock rate of 12LLC (transparent data transfer with bit TTR = 1). In general: the scaling capability of the SAA7196 can be used in various applications. 7.4.9 DATA BURST TRANSFER MODE
Data transfer on the VRAM port is asynchronously (TTR = 0). This mode can be used for all output formats. Four signals for communication with the external memory are provided: * HFL flag: the half-full flag of the FIFO output register is raised when the FIFO contains at least 8 data words (HFL = HIGH). By setting HFL = 1, the SAA7196 requests a data burst transfer by the external memory controller, that has to start a transfer cycle within the next 32 LLC cycles for 32-bit long word modes (16 LLC cycles for 16- and 24-bit modes). If there are pixels in the FIFO at the end of the line, which are not transferred, the circuit fills up the FIFO register with `fill pixels' until it is half-full and sets the HFL flag to request a data burst transfer. After transfer is done, HFL is used in combination with INCADR to indicate the line increments (see Fig.13). * INCADR output signal is used in combination with HFL to control horizontal and vertical address generation for a memory controller. The pulse sequence depends on field formats (interlace/non-interlaced or odd/even fields, see Figs 14 and 15) and control bits OF1 and OF0 (subaddress 20). * VCLK input signal to clock the FIFO register output data VRO(n). New data are placed on the VRO(n) port with the rising edge of VCLK (see Fig.13). * VOE input enables output data VRO(n). The outputs are in 3-state mode at VOE = HIGH. VOE changes only when VCLK is LOW. If VCLK pulses are applied during VOE = HIGH, the outputs remain inactive, but the FIFO register accepts the pulses.
The output FIFO register is the buffer between the video data stream and the VRAM data input port. Resized video data are buffered and formatted. 32-, 24- and 16-bit video data modes are supported. The various formats are selected by the bits EFE, VOF, FS1 and FS0. VRAM port formats are shown in Tables 7, 8 and 9. The FIFO register capacity is 16 words x 32-bit (for 32-, 24- or 16-bit video data). The bits LW1 and LW0 can be used to define the position of the first pixel each line in the 32-bit long word format or to shift the UV sequence to VU in the 16-bit YUV formats. In case of YUV output, an odd pixel count XD results in an incomplete pair of UV data at the end (LW = 0) or beginning (LW = 2) of a line. VRAM port inputs: * VMUX, the VRAM output multiplexing signal * VCLK to clock the FIFO register output data * VOE to enable output data. VRAM port outputs: * HFL flag (half-full flag) * INCADR (refer to Section 7.4.9) * VRO31 to VRO0 VRAM port output data * The reference signals for pixel and line selection on outputs VRO7 to VRO0 (only for 24- and 16-bit video data formats refer to Section 7.4.10). 1996 Nov 04 25 I2C
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
It means: HFL = 1 at the rising edge of INCADR: the `end of line' is reached; request for line address increment HFL = 0 at the rising edge of INCADR: the `end of field/frame' is reached; request for line and pixel address reset. 7.4.10 TRANSPARENT DATA TRANSFER MODE
SAA7196
Interlaced processing (OF bits, subaddress 20)
7.4.10.1
To support correct interlaced data storage, the scaler delivers two INCADR/HFL sequences in each qualified line and an additional INCADR/HFL sequence after the vertical reset sequence at the beginning of an ODD field. Thereby, the scaled lines are automatically stored in the right sequence.
Data transfer on the VRAM port can be achieved synchronously (TTR = 1) controlled by output reference signals on outputs VRO7 to VRO0, and a continuous clock rate of 12LLC on input VCLK. The SAA7196 delivers a continuously processed data stream. Therefore, the extended formats of the VRAM output port are selected (bit EFE = 1; see Table 10). The output signals VRO7 to VRO0 have to be used to buffer qualified preprocessed RGB or YUV video data. To avoid read/write collision at the internal FIFO, the VCLK timing and polarity must accord to the CREFB specification. The YUV data is only valid in qualified time slots. Control output signals are (see Table 10 and Fig.16): * : keying signal of the chroma keyer * O/E: odd/even field bit according to the internal field processing * VGT: vertical gate signal, `1' marks the scaling window in vertical direction from YO to (YO + YS) lines, cut by VS * HGT: horizontal gate signal, `1' marks horizontal direction from XO to (XO + XS) lines, cut by HREF * HRF: delay compensated horizontal reference signal * LNQ: line qualifier signal, active polarity is defined by bit QPL * PXQ: pixel qualifier signal, active polarity is defined by bit QPP.
7.4.10.2
INCADR timing
The distance from the last half-full request (HFL) to the INCADR pulse may be longer than 64 x LLC. The state of HFL is defined for minimum 2 x LLC afterwards.
7.4.10.3
Monochrome format (see Table 10)
In case of TTR = 1 and EFE = 1 is Ya = Yb.
7.4.10.4
Table 7
VRAM port specifications
VMUX control; note 1 VOE (PIN 53) 0 0 0 1 VMUX (PIN 46) 0 1 X X VRAM BUS VRO31 to VRO16 3-state active active 3-state VRO15 to VRO0 active 3-state active 3-state
BIT VOF 0 0 1 X Note 1. X = don't care. 1996 Nov 04
26
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
Table 8 VRAM port output data formats for bits 31 to 16 (continued in Table 9)
SAA7196
EFE-bit = 0 and VOF-bit = 1 (controllable via I2C-bus); burst mode only; note 1. FS1 = 0; FS0 = 0 RGB 5-5-5+ 32-BIT WORDS n VRO31 VRO30 VRO29 VRO28 VRO27 VRO26 VRO25 VRO24 VRO23 VRO22 VRO21 VRO20 VRO19 VRO18 VRO17 VRO16 Note 1. = keying bit; R, G, B, Y, U and V = digital signals; e = even pixel number; o = odd pixel number; a, b, c, d = consecutive pixels. R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+2 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+4 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 FS1 = 0; FS0 = 0 YUV 4 : 2 : 2 32-BIT WORDS n Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n+2 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n+4 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 FS1 = 0; FS0 = 0 YUV 4 : 2 : 2 16-BIT WORDS n Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n+1 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 n+2 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 FS1 = 0; FS0 = 0 8-bit monochrome 32-BIT WORDS n n+1 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 n+4 n+5 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 n+8 n+9 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0
PIXEL OUTPUT BIT
1996 Nov 04
27
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
Table 9 VRAM port output data formats for bits 15 to 0 (continued from Table 8)
SAA7196
EFE-bit = 0 and VOF-bit = 1 (controllable via I2C-bus); burst mode only; note 1. FS1 = 0; FS0 = 0 RGB 5-5-5+ 32-BIT WORDS n+1 VRO15 VRO14 VRO13 VRO12 VRO11 VRO10 VRO9 VRO8 VRO7 VRO6 VRO5 VRO4 VRO3 VRO2 VRO1 VRO0 Note 1. = keying bit; R, G, B, Y, U and V = digital signals; e = even pixel number; o = odd pixel number; a, b, c, d = consecutive pixels. R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+3 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+5 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 FS1 = 0; FS0 = 0 YUV 4 : 2 : 2 32-BIT WORDS n+1 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 n+3 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 n+5 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 FS1 = 0; FS0 = 0 YUV 4 : 2 : 2 16-BIT WORDS OUTPUTS NOT USED X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X FS1 = 0; FS0 = 0 8-bit monochrome 32-BIT WORDS n+2 n+3 Yc7 Yc6 Yc5 Yc4 Yc3 Yc2 Yc1 Yc0 Yd7 Yd6 Yd5 Yd4 Yd3 Yd2 Yd1 Yd0 n+6 n+7 Yc7 Yc6 Yc5 Yc4 Yc3 Yc2 Yc1 Yc0 Yd7 Yd6 Yd5 Yd4 Yd3 Yd2 Yd1 Yd0 n + 10 n + 11 Yc7 Yc6 Yc5 Yc4 Yc3 Yc2 Yc1 Yc0 Yd7 Yd6 Yd5 Yd4 Yd3 Yd2 Yd1 Yd0
PIXEL OUTPUT BIT
1996 Nov 04
28
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
Table 10 VRAM port output data formats for bits 31 to 16 (continued in Table 11) EFE-bit = 1 and VOF-bit = 1 (controllable via I2C-bus); burst- and transparent- modes; notes 1 to 3. FS1 = 0; FS0 = 0 RGB 5-5-5+(1) 16-BIT WORDS n VRO31 VRO30 VRO29 VRO28 VRO27 VRO26 VRO25 VRO24 VRO23 VRO22 VRO21 VRO20 VRO19 VRO18 VRO17 VRO16 Notes 1. = keying bit; R, G, B, Y, U and V = digital signals; e = even pixel number; o = odd pixel number; a and b = consecutive pixels; O/E = odd/even flag. R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+1 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+2 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 FS1 = 0; FS0 = 1 YUV 4 : 2 : 2 16-BIT WORDS n Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n+1 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 n+2 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 FS1 = 1; FS0 = 0 RGB 8-8-8 24-BIT WORDS n R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 n+1 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 n+2 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0
SAA7196
PIXEL OUTPUT BIT
FS1 = 1; FS0 = 1 8-bit monochrome 16-BIT WORDS n n+1 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 n+2 n+3 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 n+4 n+5 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0
2. YUV 16-bit format: the keying signal is defined only for YU time steps. The corresponding YV sample has also to be keyed. The signal in monochrome mode can be used only in the transparent mode (TTR = 1), in this case Ya = Yb. 3. Data valid only when transparent mode active (bit TTR = 1) and VCLK pin connected to 12LLC clock rate.
1996 Nov 04
29
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
Table 11 VRAM port output data formats for bits 15 to 0 (continued from Table 10) EFE-bit = 1 and VOF-bit = 1 (controllable via I2C-bus); burst- and transparent- modes; notes 1 to 3. FS1 = 0; FS0 = 0 RGB 5-5-5+ 16-BIT WORDS n VRO15 VRO14 VRO13 VRO12 VRO11 VRO10 VRO9 VRO8 VRO7 VRO6 VRO5 VRO4 VRO3 VRO2 VRO1 VRO0 Notes 1. = keying bit; R, G, B, Y, U and V = digital signals; e = even pixel number; o = odd pixel number; a and b = consecutive pixels; O/E = odd/even flag. X X X X X X X X O/E VGT HGT X HRF LNQ PXQ n+1 X X X X X X X X O/E VGT HGT X HRF LNQ PXQ n+2 X X X X X X X X O/E VGT HGT X HRF LNQ PXQ FS1 = 0; FS0 = 1 YUV 4 : 2 : 2 16-BIT WORDS n X X X X X X X X O/E VGT HGT X HRF LNQ PXQ n+1 X X X X X X X X X O/E VGT HGT X HRF LNQ PXQ n+2 X X X X X X X X O/E VGT HGT X HRF LNQ PXQ FS1 = 1; FS0 = 0 RGB 8-8-8 24-BIT WORDS n B7 B6 B5 B4 B3 B2 B1 B0 O/E VGT HGT X HRF LNQ PXQ n+1 B7 B6 B5 B4 B3 B2 B1 B0 O/E VGT HGT X HRF LNQ PXQ n+2 B7 B6 B5 B4 B3 B2 B1 B0 O/E VGT HGT X HRF LNQ PXQ
SAA7196
PIXEL OUTPUT BIT
FS1 = 1; FS0 = 1 8-bit monochrome 16-BIT WORDS n n+1 X X X X X X X X O/E VGT HGT X HRF LNQ PXQ n+2 n+3 X X X X X X X X O/E VGT HGT X HRF LNQ PXQ n+4 n+5 X X X X X X X X O/E VGT HGT X HRF LNQ PXQ
2. YUV 16-bit format: the keying signal is defined only for YU time steps. The corresponding YV sample has also to be keyed. The signal in monochrome mode can be used only in the transparent mode (TTR = 1), in this case Ya = Yb. 3. Data valid only when transparent mode active (bit TTR = 1) and VCLK pin connected to 12LLC clock rate.
1996 Nov 04
30
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
Table 12 VRAM port output formats for bits 31 to 16 (continued in Table 13) EFE-bit = 0 and VOF-bit = 0 (controllable via I2C-bus); burst mode only; note 1. VMUX FS1 = 0; FS0 = 0 RGB 5-5-5+ 16-BIT LONG WORD n 1 VRO31 VRO30 VRO29 VRO28 VRO27 VRO26 VRO25 VRO24 VRO23 VRO22 VRO21 VRO20 VRO19 VRO18 VRO17 VRO16 Note 1. = keying bit; R, G, B, Y, U and V = digital signals; e = even pixel number; o = odd pixel number; a, b, c, d = consecutive pixels; Z = high-impedance (3-state). R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 1 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 n+2 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 1 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 FS1 = 0; FS0 = 1 YUV 4 : 2 : 2 16-BIT WORDS n 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 1 Ye7 Ye6 Ye5 Ye4 Ye3 Ye2 Ye1 Ye0 Ue7 Ue6 Ue5 Ue4 Ue3 Ue2 Ue1 Ue0 n+2 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 1 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0
SAA7196
PIXEL OUTPUT BIT
FS1 = 1; FS0 = 1 8-bit monochrome 16-BIT WORDS n n+1 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 1 Ya7 Ya6 Ya5 Ya4 Ya3 Ya2 Ya1 Ya0 Yb7 Yb6 Yb5 Yb4 Yb3 Yb2 Yb1 Yb0 n+4 n+5 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
1996 Nov 04
31
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
Table 13 VRAM port output data formats for bits 15 to 0 (continued from Table 12) EFE-bit = 0 and VOF-bit = 0 (controllable via I2C-bus); burst mode only; note 1. VMUX FS1 = 0; FS0 = 0 RGB 5-5-5+ 16-BIT LONG WORD n+1 1 VRO15 VRO14 VRO13 VRO12 VRO11 VRO10 VRO9 VRO8 VRO7 VRO6 VRO5 VRO4 VRO3 VRO2 VRO1 VRO0 Note 1. = keying bit; R, G, B, Y, U and V = digital signals; e = even pixel number; o = odd pixel number; a, b, c, d = consecutive pixels; Z = high-impedance (3-state). Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 1 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z n+3 0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 1 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z FS1 = 0; FS0 = 1 YUV 4 : 2 : 2 16-BIT WORDS n+1 0 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 1 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z n+3 0 Yo7 Yo6 Yo5 Yo4 Yo3 Yo2 Yo1 Yo0 Ve7 Ve6 Ve5 Ve4 Ve3 Ve2 Ve1 Ve0 1 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
SAA7196
PIXEL OUTPUT BIT
FS1 = 1; FS0 = 1 8-bit monochrome 16-BIT WORDS n+2 n+3 0 Yc7 Yc6 Yc5 Yc4 Yc3 Yc2 Yc1 Yc0 Yd7 Yd6 Yd5 Yd4 Yd3 Yd2 Yd1 Yd0 1 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z n+6 n+7 0 Yc7 Yc6 Yc5 Yc4 Yc3 Yc2 Yc1 Yc0 Yd7 Yd6 Yd5 Yd4 Yd3 Yd2 Yd1 Yd0
1996 Nov 04
32
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, fullPIXCLK pagewidth
1/2LLC FIFO memory filling level
7
8
9
8
8
7
6
6
5
4
4
HFL note 1 note 2 VCLK note 3 VOE
VRO(n)
7
0
1
2
3
4
5
6
7
MHA393
(1) Minimum 8 words available in FIFO. (2) Maximum 32LLC (16PIXCLK). (3) 1 transfer cycle (8 VCLK cycles).
Fig.13 Output port transfer to VRAM at 32-bit data format without scaling. If VCLK cycles occur at VOE = HIGH, the FIFO register is unchanged, but the outputs VRO31 to VRO0 remain in 3-state position.
handbook, full pagewidth
line n
line n + 1 vertical blanking
internal signal
active video last half-full request for line n
(1)
HFL 64LLC 64LLC INCADR
(1)
min. set-up time
10LLC
line increment seqence vertical reset pulse
MHA394
(1) Only available for interlaced processing at the beginning of an odd field.
Fig.14 Vertical reset timing to the VRAM.
1996 Nov 04
33
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, full pagewidth
line n
line n + 1 horizontal blanking
internal signal
active video last half-full request for line n
(1)
active video first half-full request for line n + 1
HFL 6LLC 6LLC
64LLC INCADR
minimum set-up time
(1)
64LLC 2LLC 10LLC
line increment (VRAM)
MHA395
(1) Pulse only at interlace scan.
Fig.15 Horizontal increment timing to the VRAM.
handbook, full pagewidth
LNQ line qualifier LNQ VS HGT = GTH x LNQ HRF GTH PXQ VGT ACTIVE VIDEO WINDOW
SCALING WINDOW
field/frame
line
MHA396
Fig.16 Reference signals for scaling window.
1996 Nov 04
34
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, full pagewidth
EXTERNAL RESET, VPE = 0
VERTICAL SYNC DETECTED yes
no
COEFFICIENT UPDATE
VPE = 1 yes DO VERTICAL RESET
no
yes
VERTICAL SYNC DETECTED no
yes
CURRENT LINE IN ACTIVE REGION
no
CURRENT LINE IN BYPASS REGION yes SET SCALING ACTIVE IN CONTROL STAGE SET BYPASS MODE IN CONTROL STAGE
no
PROCESS A LINE
MHA397
Fig.17 Operation cycle.
1996 Nov 04
35
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
7.4.11 FIELD PROCESSING
SAA7196
The phase of the field sequence (odd/even dependent on inputs HREF and VS) is detected by means of the falling edge of VS. The current field phase is reported in the status byte by bit OEF (see Table 14). Bit OEF can be stable 0 or 1 for non-interlaced input frames or non-standard input signals VS and/or HREF (nominal condition for VS and HREF; SAA7196 with active vertical noise limiter). A free-running odd/even flag is generated for internal field processing if the detection reports a stable bit OEF. Bit POE (subaddress 0B) can be used to change the polarity of the internal flag (in case of non-standard VS and HREF signals) to control the phase of the free-running flag and to compensate mis-detections. Thus, the SAA7196 can be used under various VS/HREF timing conditions. The SAA7196 operates on fields. To support progressive displays and to avoid movement blurring and artifacts, the circuit can process both or single fields of interlaced or non-interlaced input data. Therefore the OF bits can be used. Bits OF1 and OF0 (see Table 30) determine the INCADR/HFL generation in `data burst transfer mode'. One of the fields (odd or even) is ignored when OF1 = 1; then no line increment sequence (INCADR/HFL) is generated, the vertical reset pulse is only generated. With OF1 = OF0 = 0 the circuit supports correct interlaced data storage (see section 7.4.10.1). 7.4.12 OPERATION CYCLE
Line processing starts when a line is decided to be active, the circuit starts to scale it. Active pixels are loaded into the FIFO register. An HFL flag is generated to initialize a data transfer when eight words are completed. The end of a line is reached when the programmed pixel number is processed or when a horizontal sync pulse occurs. If there are pixels in the FIFO register, it is filled up until it is half-full to cause a data transfer. Horizontal increment pulses are transmitted after this data transfer. The scaler part will always wait for the HREF/VS pulse before the line increment/vertical reset sequence is performed. After each line/field, the FIFO control is set to empty when the increment/vertical reset pulses are transmitted. No additional actions are necessary if the memory controller has ignored the HFL signal. There is no need to handle over-/underflow of the FIFO register. 7.5 Power-on reset
Power-on reset is activated at power-on or when the supply voltage decreases below 3.5 V. The indicator output RES is LOW for a time. The RES signal can be applied to reset other circuits of the digital TV system. * Bits VTRC and SSTB in subaddress `0DH' are set to zero * All bits in subaddress `0EH' are set to zero * The FIFO register contents are undefined * Outputs VRO, YUV, CREFB, LLCB, HREF, HS and VS are set to 3-state * Output INCADR = HIGH * Output HFL = LOW until bit VPE is set to `1' * Subaddress `30' is set to 00H and bit VPE in subaddress `20H' is set to zero (see Table 29).
The operation is synchronized by the input field. The cycle is specified in the flow chart (see Fig.17). The circuit is inactive after power-on reset, VPE = 0 and the FIFO control is set `empty'. The internal control registers are updated with the falling edge of the VS signal. The circuit is switched active and waits for a transmission of VS and a vertical reset sequence to the memory controller. Afterwards, the scaler waits for the beginning of a scaling or bypass region. If the active scaling region begins, while the bypass region is active, the bypass region is interrupted. If a vertical sync appears, the processing of the current line is finished. Then, the scaler performs a coefficient update and generates a new vertical reset (if it is still active).
1996 Nov 04
36
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
8 8.1 S(1) Notes 1. START condition. PROGRAMMING MODEL I2C-bus format SLAVE ADDRESS(2) A(3) SUBADDRESS(4) A(3) DATA0(5) A(3)
SAA7196
DATAn(5)
A(3) P(6)
2. 0100 000X (I2CSA = LOW) or 0100 001X (I2CSA = HIGH); X = read/write control bit [X = 0: order to write (the circuit is slave receiver); X = 1: order to read (the circuit is slave transmitter)]. 3. Acknowledge, generated by the slave. 4. Subaddress byte (see Tables 16 to 30); if more than 1 byte data is transmitted, auto-increment of the subaddress is performed. 5. DATA byte (see Tables 16 to 30). 6. STOP condition.
1996 Nov 04
37
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
8.2 I2C-bus status information
SAA7196
Table 14 I2C-bus status byte (X in address byte = 1; 41H at I2CSA = LOW or 43H at I2CSA = HIGH); see Table 15 DATA FUNCTION D7 Status byte 0 (transmitted after RES = 0 or at SSTB = 0) Status byte 1 (transmitted at SSTB = 1) Table 15 Function of status bits; note 1 BIT DIR FUNCTION state of input DIR (pin 95): direction control of expansion port YUV DIR = 0: the scaler uses internal source (decoder output) DIR = 1: the scaler uses external data of expansion bus OEF identification of field sequence dependent on HREF and VS 0 = even field detected 1 = odd field detected SVP state of VRAM port (state of, bit VPE cleared by RES) 0 = inputs HFL and INCADR inactive 1 = inputs HFL and INCADR active STTC horizontal time constant information (for future application with logical comb-filter only) 0 = TV time constant (slow) 1 = VCR time constant (fast) HLCK horizontal PLL information 0 = HPLL locked 1 = HPLL unlocked FIDT field information 0 = 50 Hz system detected 1 = 60 Hz system detected ALTD line alternation 0 = no line alternating colour burst detected 1 = line alternating colour burst detected (PAL or SECAM) CODE colour information 0 = no colour detected 1 = colour detected X Note 1. Software model of SAA7196 compatible with ID3 to ID0 = 0; version V0 (first version). for future enhancements, do not evaluate ID3 STTC D6 ID2 HLCK D5 ID1 FIDT D4 ID0 X D3 DIR X D2 X X D1 OEF ALTD D0 SVP CODE
1996 Nov 04
38
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
8.3 Decoder part
SAA7196
Table 16 I2C-bus decoder control; subaddress and data bytes for writing (X in address byte = 0; 40H at I2CSA = LOW or 42H at I2CSA = HIGH) DATA FUNCTION SUBADDRESS D7 Increment delay H-sync begin; 50 Hz H-sync stop; 50 Hz H-clamp begin; 50 Hz H-clamp stop; 50 Hz H-sync after PHI1; 50 Hz Luminance control Hue control Colour-killer QUAM Colour-killer SECAM PAL switch sensitivity Chroma gain control Standard/mode control I/O and clock control Control #1 Control #2 Chroma gain reference Chroma saturation Luminance contrast H-sync begin; 60 Hz H-sync stop; 60 Hz H-clamp begin; 60 Hz H-clamp stop; 60 Hz H-sync after PHI1: 60 Hz Luminance brightness Reserved 00 01 02 03 04 05 06 07 08 09 0A 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A to 1F IDEL7 HSYB7 HSYS7 HCLB7 HCLS7 HPHI7 BYPS HUEC7 CKTQ4 CKTS4 PLSE7 SESE7 COLO VTRC HPLL AUFD 0 CHCV7 0 0 HS6B7 HS6B7 HC6B7 HC6S7 HP6I7 BRIG7 0 D6 IDEL6 HSYB6 HSYS6 HCLB6 HCLS6 HPHI6 PREF HUEC6 CKTQ3 CKTS3 PLSE6 SESE6 LFIS1 0 0 FSEL 0 CHCV6 SATN6 CONT6 HS6B7 HS6B7 HC6B7 HC6S7 HP6I6 BRIG6 0 D5 IDEL5 HSYB5 HSYS5 HCLB5 HCLS5 HPHI5 BPSS1 HUEC5 CKTQ2 CKTS2 PLSE5 SESE5 LFIS0 0 OECL SXCR 0 CHCV5 SATN5 CONT5 HS6B7 HS6B7 HC6B7 HC6S7 HP6I5 BRIG5 0 D4 IDEL4 HSYB4 HSYS4 HCLB4 HCLS4 HPHI4 BPSS0 HUEC4 CKTQ1 CKTS1 PLSE4 SESE4 0 0 OEHV SCEN 0 CHCV4 SATN4 CONT4 HS6B7 HS6B7 HC6B7 HC6S7 HP6I4 BRIG4 0 D3 IDEL3 HSYB3 HSYS3 HCLB3 HCLS3 HPHI3 CORI1 HUEC3 CKTQ0 CKTS0 PLSE3 SESE3 0 RTSE OEYC 0 0 CHCV3 SATN3 CONT3 HS6B7 HS6B7 HC6B7 HC6S7 HP6I3 BRIG3 0 D2 IDEL2 HSYB2 HSYS2 HCLB2 HCLS2 HPHI2 CORI0 HUEC2 0 0 PLSE2 SESE2 0 HRMV CHRS YDEL2 HRFS CHCV2 SATN2 CONT2 HS6B7 HS6B7 HC6B7 HC6S7 HP6I2 BRIG2 0 D1 IDEL1 HSYB1 HSYS1 HCLB1 HCLS1 HPHI1 APER1 HUEC1 0 0 PLSE1 SESE1 0 SSTB YDEL1 VNOI1 CHCV1 SATN1 CONT1 HS6B7 HS6B7 HC6B7 HC6S7 HP6I1 BRIG1 0 D0 IDEL0 HSYB0 HSYS0 HCLB0 HCLS0 HPHI0 APER0 HUEC0 0 0 PLSE0 SESE0 0 SECS YDEL0 VNOI0 CHCV0 SATN0 CONT0 HS6B7 HS6B7 HC6B7 HC6S7 HP6I0 BRIG0 0 DF(1)
SECAM switch sensitivity 0B
GPSW2 GPSW1
Note 1. Default register contents to be filled in by hand.
1996 Nov 04
39
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
Table 17 Function of the register bits of Table 16 for subaddresses `00' to `19' SUBADDRESS IDEL7 to IDEL0 `00' DESCRIPTION
SAA7196
Increment delay time (dependent on application), step size = 4/LLC. The delay time is selectable from -4/LLC (-1 decimal multiplier) to -1024/LLC (-256 decimal multiplier) equals data FFH to 00H. A sign-bit, designated A08 and internally set HIGH, indicates always negative values. The maximum delay time in 60 Hz systems is -780 equally to 3DH; the maximum delay time in 50 Hz systems is -944 equally to 14H. Different processing times in the chrominance channel and the clock generation could result in phase errors in the chrominance processing by transients in clock frequency. An adjustable delay (IDEL) is necessary if the processing time in the clock generation is unknown (the horizontal PLL does not operate if the maximum delays are exceeded; the system clock frequency is set to a value of the last update and is within 7.1% of nominal frequency).
HSYB7 to HSYB0 `01'
Horizontal sync begin for 50 Hz, step size = 2/LLC. The delay time is selectable from -382/LLC (+191 decimal multiplier) to +128/LLC (-64 decimal multiplier) and equals data BFH to C0H. Two's complement numbers with `hidden' sign-bit. The sign-bit is generated internally by evaluating the MSB and the MSB-1 bits. Horizontal sync stop for 50 Hz, step size = 2/LLC. The delay time is selectable from -382/LLC (+191 decimal multiplier) to +128/LLC (-64 decimal multiplier) equals data BFH to C0H. Two's complement numbers with `hidden' sign-bit. The sign-bit is generated internally by evaluating the MSB and the MSB-1 bits. Horizontal clamp start for 50 Hz, step size = 2/LLC. The delay time is selectable from -254/LLC (+127 decimal multiplier) to +256/LLC (-128 decimal multiplier) equals data 7FH to 80H. Horizontal clamp stop for 50 Hz, step size = 2/LLC. The delay time is selectable from -254/LLC (+127 decimal multiplier) to +256/LLC (-128 decimal multiplier) equals data 7FH to 80H. Horizontal sync start after PHI1 for 50 Hz, step size = 8/LLC. The delay time is selectable from -32 to +31.7 s (+118 to -118 decimal multiplier) equals data 75H to 8AH . Forbidden, outside available central counter range, are +127 to +118 decimal multiplier equals data 7EH to 76H as well as -119 to -128 decimal multiplier equals data 89H to 80H. input mode select bit 0 = CVBS mode (chrominance trap active) 1 = S-Video mode (chrominance trap bypassed) use of prefilter 0 = prefilter off (bypassed) 1 = prefilter on; PREF may be used if chrominance trap is active Aperture band-pass to select different characteristics with maximums (0.2 to 0.3 x LLC/2); see Table 18 and Figs 19 to 28. Coring range for high frequency components according to 8-bit luminance; see Table 19 and Fig.18. Aperture band-pass filter weights high frequency components of luminance signal; see Table 20 and Figs 19 to 28. Hue control from +178.6 to -180.0 equals data bytes 7FH to 80H; 0 equals 00.
HSYS7 to HSYS0 `02'
HCLB7 to HCLB0 `03' HCLS7 to HCLS0 `04' HPHI7 to HPHI0 `05'
BYPS `06'
PREF `06'
BPSS1 to BPSS0 `06' CORI1 to CORI0 `06' APER1 and APER0 `06' HUE7 to HUE0 `07' 1996 Nov 04
40
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SUBADDRESS CKTQ4 to CKTQ0 `08' CKTS4 to CKTS0 `09' PLSE7 to PLSE0 `0A' SESE7 to SESE0 `0B' COLO `0C' DESCRIPTION
SAA7196
Colour-killer threshold QAM (PAL, NTSC) from approximately -30 dB to -18 dB equals data bytes F8H to 07H. Colour-killer threshold SECAM from approximately -30 dB to -18 dB equals data bytes F8H to 07H. PAL switch sensitivity from LOW to HIGH (HIGH means immediate sequence correction) equals FFH to 00H, MEDIUM equals 80. SECAM switch sensitivity from LOW to HIGH (HIGH means immediate sequence correction) equals FFH to 00H, MEDIUM equals 80. colour-on bit 0 = automatic colour-killer 1 = forced colour-on Automatic gain control (AGC filter); see Table 21. VTR/TV mode bit 0 = TV mode 1 = VTR mode real time output mode select bit 0 = PLIN switched to output RTS1 (pin 34); ODD switched to RTS0 (pin 35) 1 = HL switched to output RTS1 (pin 34); VL switched to RTS0 (pin 35) HREF position select 0 = default 1 = HREF is 8 x LLC2 clocks earlier status byte select 0 = status byte 0 is selected 1 = status byte 1 is selected
LFIS1 to LFIS0 `0C' VTRC `0D'
RTSE `0D'
HRMV `0D'
SSTB
SECS `0D'
SECAM mode bit 0 = other standards 1 = SECAM horizontal clock PLL 0 = PLL closed 1 = PLL open and horizontal frequency fixed select internal/external clock source 0 = LLCB and CREFB are inputs 1 = LLCB and CREFB are outputs output enable of horizontal/vertical sync 0 = HS, HREF and VS pins are inputs (outputs high-impedance) 1 = HS, HREF and VS pins are outputs data output YUV15 to YUV0 enable 0 = data pins are inputs 1 = data pins are controlled by DIR (pin 95)
HPLL `0E'
OECL `0E'
OEHV `0E'
OEYC `0E'
1996 Nov 04
41
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SUBADDRESS CHRS `0E' DESCRIPTION S-VHS bit (chrominance from CVBS or from chrominance input) 0 = controlled by bit BYPS (subaddress 06) 1 = chrominance from chrominance input CHR7 to CHR0 GPSW2 and GPSW1 `0E' AUFD `0F' general purpose switches; see Table 22 automatic field detection 0 = field selection by bit FSEL 1 = automatic field detection by SAA7196 FSEL `0F' field select (bit AUFD = 0) 0 = 50 Hz (625 lines) 1 = 60 Hz (525 lines) SXCR `0F' SECAM cross-colour reduction 0 = reduction off 1 = reduction on SCEN `0F' enable sync and clamping pulse 0 = HSY and HCL outputs HIGH (pins 25 and 26) 1 = HSY and HCL outputs active YDEL2 to YDEL0 `0F' HRFS `10' luminance delay compensation; see Table 23 select HREF position 0 = normal, HREF is matched to YUV output on expansion port 1 = HREF is matched to CVBS input port VNOI1 to VNOI0 `10' CHCV7 to CHCV0 `11' SATN6 to SATN0 `12' CONT6 to CONT0 `13' HS6B7 to HS6B0 `14' vertical noise reduction; see Table 24
SAA7196
chrominance gain control (nominal values) for QAM-modulated input signals, effects UV output amplitude (SECAM with fixed gain); see Table 25 chrominance saturation control for VRAM port; see Table 26 luminance contrast control for VRAM port; see Table 27 Horizontal sync begin for 60 Hz, step size = 2/LLC. The delay time is selectable from -382/LLC (+191 decimal multiplier) to +128/LLC (-64 decimal multiplier) equals data BFH to C0H. Two's complement numbers with `hidden' sign-bit. The sign-bit is generated internally by evaluating the MSB and the MSB-1 bits. Horizontal sync stop for 60 Hz, step size = 2/LLC. The delay time is selectable from -382/LLC (+191 decimal multiplier) to +128/LLC (-64 decimal multiplier) equals data BFH to C0H. Two's complement numbers with `hidden' sign-bit. The sign-bit is generated internally by evaluating the MSB and the MSB-1 bits. Horizontal clamp begin for 60 Hz, step size = 2/LLC. The delay time is selectable from -254/LLC (+127 decimal multiplier) to +256/LLC (-128 decimal multiplier) and equals data 7FH to 80H.
HS6S7 to HS6S0 `15'
HC6B7 to HC6B0 `16'
1996 Nov 04
42
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SUBADDRESS HC6S7 to HC6S0 `17' HP6I7 to HP6I0 `18' DESCRIPTION
SAA7196
Horizontal clamp stop for 60 Hz, step size = 2/LLC. The delay time is selectable from -254/LLC (+127 decimal multiplier) to +256/LLC (-128 decimal multiplier) equals data 7FH to 80H. Horizontal sync start after PHI1 for 60 Hz, step size = 8/LLC. The delay time is selectable from -32 to +31.7 s (+97 to -97 decimal multiplier) equals data 61H to 9FH. Forbidden, outside available central counter range, are +127 to +98 decimal multiplier equals data 7EH to 62H as well as -98 to -128 decimal multiplier equals data 9EH to 80H. luminance brightness control for VRAM port; see Table 28
BRIG7 to BRIG0 `19'
Table 18 Aperture band-pass to select different characteristics with maximums (0.2 to 0.3 x 12LLC); for characteristics see Figs 19 to 28 BIT BPSS1 0 0 1 1 Table 19 Coring range for high frequency components according to 8-bit luminance BIT CORING CORI1 0 0 1 1 CORI0 0 1 0 1 coring off 1 LSB of 8-bit 2 LSB of 8-bit 3 LSB of 8-bit BPSS0 0 1 0 1
Table 20 Aperture band-pass filter weights high frequency components of luminance signal; for characteristics see Figs 19 to 28 BIT FACTOR APER1 0 0 1 1 APER0 0 1 0 1 0 0.25 0.5 1
1996 Nov 04
43
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
Table 21 Automatic gain control (AGC filter) BIT
SAA7196
LOOP FILTER TIME CONSTANT LFIS1 0 0 1 1 LFIS0 0 1 0 1 slow medium fast actual gain stored (for test purposes only)
Table 22 General purpose switches BIT SET PORT OUTPUT PINS GPSW2 (PIN 32) 0 0 1 1 Table 23 Luminance delay compensation BIT YDEL2 0 0 0 0 1 1 1 1 Note 1. Step size = 2/LCC = 67.8 ns for 50 Hz and 81.5 ns for 60 Hz. YDEL1 0 0 1 1 0 0 1 1 YDEL0 0 1 0 1 0 1 0 1 0 x 2/LCC +1 x 2/LCC +2 x 2/LCC +3 x 2/LCC -4 x 2/LCC -3 x 2/LCC -2 x 2/LCC -1 x 2/LCC DELAY(1) GPSW1 (PIN 33) 0 1 0 1 use is dependent on application
1996 Nov 04
44
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
Table 24 Vertical noise reduction BIT
SAA7196
MODE VNOI1 0 0 1 1 Table 25 Chrominance gain control; note 1 BIT GAIN D7 1 . 0 . 0 . 0 Note 1. Default programmed values dependent on application. D6 1 . 1 . 0 . 0 D5 1 . 0 . 1 . 0 D4 1 . 1 . 0 . 0 D3 1 . 1 . 1 . 0 D2 1 . 0 . 1 . 0 D1 1 . 0 . 0 . 0 D0 1 . 1 . 0 . 0 maximum gain to CCIR level for PAL to CCIR level for NTSC to minimum gain VNOI0 0 1 0 1 normal searching window free-running mode vertical noise reduction bypassed
1996 Nov 04
45
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
Table 26 Chrominance saturation control for VRAM port BIT GAIN D7 0 . 0 . 0 D6 1 . 1 . 0 D5 1 . 0 . 0 D4 1 . 0 . 0 D3 1 . 0 . 0 D2 1 . 0 . 0 D1 1 . 0 . 0 D0 1 . 0 . 0
SAA7196
1.999 (maximum saturation) to 1 (CCIR level) to 0 (colour off)
Table 27 Luminance contrast control for VRAM port BIT GAIN D7 0 . 0 . 0 D6 1 . 1 . 0 D5 1 . 0 . 0 D4 1 . 0 . 0 D3 1 . 0 . 0 D2 1 . 0 . 0 D1 1 . 0 . 0 D0 1 . 0 . 0 1.999 (maximum contrast) to 1 (CCIR level) to 0 (luminance off)
Table 28 Luminance brightness control for VRAM port BIT GAIN D7 1 . 1 . 0 D6 1 . 0 . 0 D5 1 . 0 . 0 D4 1 . 0 . 0 D3 1 . 0 . 0 D2 1 . 0 . 0 D1 1 . 0 . 0 D0 1 . 0 . 0 255 (bright) to 128 (CCIR level) to 0 (dark)
1996 Nov 04
46
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, halfpage
+64
MHA400
bits +32
(1) (2) (3)
0
(3) (2)
-32
(1)
-64 -64
-32
0
+32
bits +64
The tresholds are related to the 13-bit word width in the luminance processing part and influence the 1LSB to 3LSB (Y0 to Y2) with respect to the 8-bit luminance output). (1) CORI1 = 1; CORI0 = 1 (2) CORI1 = 1; CORI0 = 0 (3) CORI1 = 0; CORI0 = 1
Fig.18 Coring function adjustment by subaddress 06 to affect the band filter output signal.
1996 Nov 04
47
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, full pagewidth V
18
MHA398
Y (dB)
(4)
12 6
(3) (1) (2) (1) (2)
0 -6 -12 -18 -24 -30 0 (1) 43H. 1 (2) 53H. 2 (3) 63H. 3 (4) 73H. 4 5 fY (MHz) 6
(4) (3)
Fig.19 Luminance control in 50 Hz/CVBS mode controllable by subaddress byte 06; pre-filter on and coring off; maximum aperture band-pass filter characteristic.
handbook, full pagewidth V
18
MHA399
Y (dB)
(5)
12 6
(4)
(3)
(3)
0 -6 -12 -18 -24 -30 0 1 2 3
(2) (5) (1)
(2)
(4) (1)
4
5
fY (MHz)
6
(1) 40H.
(2) 41H.
(3) 42H.
(4) 61H.
(5) 62H.
Fig.20 Luminance control in 50 Hz/CVBS mode controllable by subaddress byte 06; pre-filter on and coring off; other aperture band-pass filter characteristic.
1996 Nov 04
48
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, full pagewidth V
18
MHA401
Y (dB)
(4)
(5)
12 6
(2) (3) (2) (5)
(3)
0 -6 -12 -18 -24 -30 0 (1) 00H. 1 (2) 03H. 2 (3) 13H. 3 (4) 23H. 4 (5) 33H. 5 fY (MHz)
(1)
(4)
(1)
6
Fig.21 Luminance control in 50 Hz/CVBS mode controllable by subaddress byte 06; pre-filter off and coring off; maximum aperture band-pass filter characteristic.
handbook, full pagewidth V
18
MHA402
Y (dB)
(4)
12 6
(3) (1) (2) (1) (2)
0 -6 -12 -18 -24 -30 0 (1) 43H. 1 (2) 53H. 2 (3) 63H. 3 (4) 73H. 4 5 fY (MHz) 6
(3) (4)
Fig.22 Luminance control in 60 Hz/CVBS mode controllable by subaddress byte 06; pre-filter on and coring off; maximum aperture band-pass filter characteristics.
1996 Nov 04
49
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, full pagewidth V
18
MHA403
Y (dB)
(4)
12
(5) (3)
6
(2) (1) (5)
(2)
(3)
0 -6
(1) (4)
-12 -18 -24 -30 0 1 2 3 4 5 fY (MHz) 6
(1) 40H.
(2) 41H.
(3) 42H.
(4) 61H.
(5) 62H.
Fig.23 Luminance control in 60 Hz/CVBS mode controllable by subaddress byte 06; pre-filter on and coring off; other aperture band-pass filter characteristics.
handbook, full pagewidth V
18
MHA404
Y (dB)
12 6
(4) (3) (2)
(5)
(2) (5)
(3)
0 -6 -12 -18 -24 -30 0 1 2 3 4
(1)
(4) (1)
5
fY (MHz)
6
(1) 00H.
(2) 03H.
(3) 13H.
(4) 23H.
(5) 33H.
Fig.24 Luminance control in 60 Hz/CVBS mode controllable by subaddress byte 06; pre-filter off and coring off; maximum and minimum aperture band-pass filter characteristics.
1996 Nov 04
50
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, halfpage V
18 Y (dB) 12
MHA405
handbook, halfpage
(4)
18 VY (dB) 12
MHA406
(3) (4) (3)
6
6
(2) (1)
0
(2)
0
(1)
-6 -12 -18 0 2 4 6 fY (MHz) 8
-6 -12 -18 0 2 4 6 fY (MHz) 8
(1) 80H.
(2) 81H.
(3) 82H.
(4) 83H.
(1) C0H.
(2) C1H.
(3) C2H.
(4) C3H.
Fig.25 Luminance control in 50 Hz/S-VHS mode controllable by subaddress byte 06; pre-filter off and coring off; different aperture band-pass filter characteristics.
Fig.26 Luminance control in 50 Hz/S-VHS mode controllable by subaddress byte 06; pre-filter on and coring off; different aperture band-pass filter characteristics.
handbook, halfpage V
18 Y (dB) 12
MHA407
handbook, halfpage V
(4)
18 Y (dB) 12
MHA408
(4)
(3)
(3)
6
6
(2) (1)
0
(2) (1)
0
-6 -12 -18 0 2 4 6 fY (MHz) 8
-6 -12 -18 0 2 4 6 fY (MHz) 8
(1) 80H.
(2) 81H.
(3) 82H.
(4) 83H.
(1) C0H.
(2) C1H.
(3) C2H.
(4) C3H.
Fig.27 Luminance control in 60 Hz/S-VHS mode controllable by subaddress byte 06; pre-filter off and coring off; different aperture band-pass filter characteristics.
Fig.28 Luminance control in 60 Hz/S-VHS mode controllable by subaddress byte 06; pre-filter on and coring off; different aperture band-pass filter characteristics.
1996 Nov 04
51
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
8.4 Scaler part
SAA7196
Table 29 I2C-bus scaler control; subaddress and data bytes for writing DATA FUNCTION SUBADDRESS D7 Formats and sequence Output data pixel/line(2) Input data pixel/line(2) Horizontal window Horizontal filter Output data lines/field(3) Input data lines/field(3) start(3) start(4) count(4) Vertical window Vertical bypass Vertical bypass Chroma keying lower limit for V upper limit for V lower limit for U upper limit for U Data path setting(5) Unused 2C 2D 2E 2F 30 31 to 3F VL7 VU7 UL7 UU7 VOF VL6 VU6 UL6 UU6 AFG VL5 VU5 UL5 UU5 LLV VL4 VU4 UL4 UU4 MCT VL3 VU3 UL3 UU3 QPL VL2 VU2 UL2 UU2 QPP VL1 VU1 UL1 UU1 TTR VL0 VU0 UL0 UU0 EFE start(2) 20 21 22 23 24 25 26 27 28 29 2A 2B RTB XD7 XS7 XO7 HF2 YD7 YS7 YO7 AFS VS7 VC7 0 D6 OF1 XD6 XS6 XO6 HF1 YD6 YS6 YO6 VP1 VS6 VC6 0 D5 OF0 XD5 XS5 XO5 HF0 YD5 YS5 YO5 VP0 VS5 VC5 0 D4 VPE XD4 XS4 XO4 XO8 YD4 YS4 YO4 YO8 VS4 VC4 VS8 D3 LW1 XD3 XS3 XO3 XS9 YD3 YS3 YO3 YS9 VS3 VC3 0 D2 LW0 XD2 XS2 XO2 XS8 YD2 YS2 YO2 YS8 VS2 VC2 VC8 D1 FS1 XD1 XS1 XO1 XD9 YD1 YS1 YO1 YD9 VS1 VC1 0 D0 FS0 XD0 XS0 XO0 XD8 YD0 YS0 YO0 YD8 VS0 VC0 POE DF(1)
AFS/vertical Y processing
Notes 1. Default register contents to be filled in by hand. 2. Continued in `24'. 3. Continued in `28'. 4. Continued in `2B'. 5. Data representation, transfer mode and adaptivity.
1996 Nov 04
52
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
Table 30 Function of the register bits of Table 29 for subaddresses `20' to `30' SUBADDRESS RTB `20' ROM table bypass switch 0 = anti-gamma ROM active 1 = table is bypassed OF1 to OF0 VPE set output field mode; see Table 31 VRAM port outputs enable DESCRIPTION
SAA7196
0 = HFL and INCADR inactive (HFL = LOW, INCADR = HIGH); VRO outputs in 3-state 1 = HFL and INCADR enabled; VRO outputs dependent on VOE LW1 to LW0 `20' first pixel position in VRO data FS1 = 0; FS0 = 0 (RGB) and FS1 = 0; FS0 = 1 (YUV); see Table 32 FS1 = 1; FS0 = 1 (monochrome); see Table 33 FS1 to FS0 XD9 to XD0 `21 and 24' XS9 to XS0 `22 and 24' XO8 to XO0 `23 and 24' HF2 to HF0 `24' YD9 to YD0 `25 and 28' YS9 to YS0 `26 and 28' FIFO output register format select (bit EFE see `30'); see Table 34 pixel number per line (straight binary) on output (VRO): 00 0000 0000 to 11 1111 1111 (number of XS pixels as a maximum; take care of vertical processing) pixel number per line (straight binary) on inputs (YIN and UVIN): 00 0000 0000 to 11 1111 1111 (number of input pixels per line as a maximum; take care of vertical processing) Horizontal start position (straight binary) of scaling window (take care of active pixel number per line): start with the 1st pixel after HREF rise = 0 0000 0011 to 1 1111 1111 (003 to 1FF). Window start and window end may be cut by internal delay compensated HREF = 0 phase. Horizontal decimation filter; the filter coefficients are related to the luminance path. The filter coefficient may differ from upper table when a combination with vertical Y processing and adaptive modes are provided. See Table 35. line number per output field (straight binary): 00 0000 0000 to 11 1111 1111 (number of YS lines as a maximum) line number per input field (straight binary) 00 0000 0000 for 0 line 11 1111 1111 for 1023 lines (maximum = number of lines/field - 3) YO8 to YO0 `27 and 28' Vertical start of scaling window [take care of active line number per field (straight binary); window start and window end may be cut by the external VS signal] 0 0000 0000; start with 3rd line after the rising slope of VS 0 0000 0011; start with 1st line after the falling slope of nominal VS (7151B, 7191B input) 1 1111 1111; 511 + 3 lines after the rising slope of VS (maximum value) AFS `28' adaptive filter switch 0 = off; use VP1, VP0 and HF2 to HF0 bits 1 = on; filter characteristics are selected by the scaler VP1 to VP0 VS8 to VS0 `29 and 2B' vertical luminance data processing; see Table 36 vertical bypass start, sets begin of the bypass region (straight binary); scaling region overrides bypass region (YO bits) 0 0000 0000; start with 3rd line after the rising slope of VS 0 0000 0011; start with 1st line after the falling slope of nominal VS (7151B, 7191B input) 1 1111 1111; 511 + 3 lines after the rising slope of VS (maximum value)
1996 Nov 04
53
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
VC8 to VC0 `29 and 2B' vertical bypass count, sets length of bypass region (straight binary) 0 0000 0000; 0 line length 1 1111 1111; 511 lines length (maximum = number of lines/field - 3) POE polarity, internally detected odd/even flag O/E 0 = flag unchanged 1 = flag inverted VL7 to VL0 `2C' set lower limit V for colour-keying (8-bit; two's complement) 1000 0000; as maximum negative value = -128 signal level 0000 0000; limit = 0 0111 1111; as maximum positive value = +127 signal level VU7 to VU0 `2D' set upper limit V for colour-keying (8-bit; two's complement) 1000 0000; as maximum negative value = -128 signal level 0000 0000; limit = 0 0111 1111; as maximum positive value = +127 signal level UL7 to UL0 `2E' set lower limit V for colour-keying (8-bit; two's complement) 1000 0000; as maximum negative value = -128 signal level 0000 0000; limit = 0 0111 1111; as maximum positive value = +127 signal level UU7 to UU0 `2F' set upper limit V for colour-keying (8-bit; two's complement) 1000 0000; as maximum negative value = -128 signal level 0000 0000; limit = 0 0111 1111; as maximum positive value = +127 signal level VOF `30' VRAM bus output format 0 = enabling of 32 to 16-bit multiplexing via VMUX (pin 46) 1 = disabling of 32 to 16-bit multiplexing via VMUX (pin 46) AFG adoptive geometrical filter 0 = linear H and V data processing
SAA7196
1 = approximated geometrical H and V interpolation (improved scaling accuracy of luminance) LLV luminance limiting value 0 = amplitude range between 1 and 254 1 = amplitude range between 16 and 235, suitable for monochrome and YUV modes MCT monochrome and two's complement output data select 0 = inverse gray scale luminance (if gray scale is selected by FIS bits) or straight binary U, V data output 1 = non-inverse monochrome luminance (if gray scale is selected by FS bits) or two's complement U, V data output QPL line qualifier polarity flag 0 = LNQ is active-LOW (pin 52) 1 = LNQ is active-HIGH
1996 Nov 04
54
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
QPP pixel qualifier polarity flag 0 = PXQ is active-LOW (pin 51) 1 = PXQ is active-HIGH TTR transparent data transfer 0 = normal operation (VRAM data burst transfer) 1 = FIFO register transparent EFE extended formats enable bit (see FS bits in subaddress `20') 0 = 32-bit long word output formats 1 = extended output formats (`one pixel a time') Table 31 Set output field mode BIT
SAA7196
MODE OF1 0 0 1 1 OF0 0 1 0 1 both fields for interlaced storage both fields for non-interlaced storage odd fields only (even fields ignored) for non-interlaced storage even fields only (odd fields ignored) for non-interlaced storage
Table 32 First pixel position in VRO data for FS1 = 0; FS0 = 0 (RGB) and FS1 = 0; FS0 = 1 (YUV) LW1 0 0 1 1 LW0 0 1 0 1 31 to 24 pixel 0 pixel 0 black black 23 to 16 pixel 0 pixel 0 black black 15 to 8 pixel 1 pixel 1 pixel 0 pixel 0 7 to 0 pixel 1 pixel 1 pixel 0 pixel 0 CONDITIONS EFE = 0; TTR = 0
Table 33 First pixel position in VRO data for FS1 = 1; FS0 = 1 (monochrome); note 1 LW1 0 0 1 1 0 0 1 1 Note 1. X = don't care. LW0 0 1 0 1 0 1 0 1 31 to 24 pixel 0 black black black pixel 0 black pixel 0 black 23 to 16 pixel 1 pixel 0 black black pixel 1 pixel 0 pixel 1 pixel 0 15 to 8 pixel 2 pixel 1 pixel 0 black X X X X 7 to 0 pixel 3 pixel 2 pixel 1 pixel 0 X X X X EFE = 1; TTR = 0; LW only effects the gray scale format CONDITIONS EFE = 0; TTR = 0
1996 Nov 04
55
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
Table 34 FIFO output register format select (bit EFE; see `30') EFE 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 OUTPUT FORMAT (Tables 8 to 11)
SAA7196
RGB 5-5-5+; 2 x 16-bit/pixel; 32-bit word length; RGB matrix on, VRAM output format YUV 4 : 2 : 2; 2 x 16-bit/pixel; 32-bit word length; RGB matrix off, VRAM output format YUV 4 : 2 : 2; 1 x 16-bit/pixel; 16-bit word length; RGB matrix off, optional output format monochrome mode; 4 x 8-bit/pixel; 32-bit word length; RGB matrix off, VRAM output format RGB 5-5-5+; 1 x 16-bit/pixel; 16-bit word length; RGB matrix on, VRAM output + transparent format YUV 4 : 2 : 2+; 1 x 16-bit/pixel; 16-bit word length; RGB matrix off, VRAM output + transparent format RGB 8-8-8+; 1 x 24-bit/pixel; 24-bit word length; RGB matrix on, VRAM output + transparent format monochrome mode; 2 x 8-bit/pixel; 16-bit word length; RGB matrix off, VRAM output + transparent format
Table 35 Horizontal decimation filter HF2 0 0 0 0 1 1 1 1 HF1 0 0 1 1 0 0 1 1 HF0 0 1 0 1 0 1 0 1 TAPS 2 3 5 9 1 1 8 4 filter 1 filter 2 filter 3 filter 4 filter bypassed filter bypassed + delay in Y channel of 1T filter 5 filter 6 FILTER (see Figs 29 and 30)
Table 36 Vertical luminance data processing VP1 0 0 1 1 VP0 0 1 0 1 bypassed delay of one line H(z) = z-H vertical filter 1: [H(z) = 12(1 + z-H)] vertical filter 2: [H(z) = 14(1 + 2z-H + z-2H)] PROCESSING (APPROXIMATE EQUATIONS)
1996 Nov 04
56
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
MHA409
handbook, full pagewidth
10
(dB)
(5) (6)
0
(3)
-10
(7) (4)
(8)
(2)
(1)
-20
-30
-40
(4) (7)
-50
0 (2) 001.
0.1 (3) 010. (4) 011.
0.2 (5) 100.
0.3 (6) 101. (7) 110.
0.4 (8) 111.
f/fCLK
0.5
(1) 000.
Fig.29 Horizontal frequency characteristic of luminance signal (Y) dependent on HF2 to HF0 bits (subaddress 24).
MHA410
handbook, full pagewidth
10
(dB) 0
(5) (6)
(1)
-10
(8)
(2)
-20
(3) (4) (7)
-30
-40
(4) (7)
-50
0
0.05
0.10
0.15
0.20
f/fCLK
0.25
(1) 000.
(2) 001.
(3) 010.
(4) 011.
(5) 100.
(6) 101.
(7) 110.
(8) 111.
Fig.30 Horizontal frequency characteristic of chrominance signals (UV) without UV interpolation dependent on HF2 to HF0 bits (subaddresses 24).
1996 Nov 04
57
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI Ves Ptot Tstg Tamb Note 1. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 10 CHARACTERISTICS VDD = 4.5 to 5.5 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL Supply VDDD VDDA IDDD IDDA VIL VIH ILI CI digital supply voltage; pins 14, 31, 45, 61, 77, 91 and 106 analog supply voltage; pin 27 digital supply current analog supply current inputs LOW; outputs without load 4.5 4.5 - - -0.5 -0.5 2.4 2.0 - - - high-impedance state - 5 5 170 10 - - - - - - - - - - 5.5 5.5 260 20 PARAMETER CONDITIONS MIN. TYP. PARAMETER supply voltage; pins 14, 27, 31, 45, 61, 77, 91 and 106 voltage on all input/output pins electrostatic handling for all pins total power dissipation storage temperature range operating ambient temperature range note 1 CONDITIONS MIN. -0.5 -0.5 - - -65 0
SAA7196
MAX. +6.5 VDD + 0.5 2000 1.5 +150 70 V V V W C C
UNIT
MAX.
UNIT
V V mA mA
Data, clock and control inputs LOW level input voltage HIGH level input voltage input leakage current input capacitance data input capacitance clocks input capacitance 3-state I/O Data and control outputs; note 1 VOL VOH Vo(p-p) V28 LOW level output voltage HIGH level output voltage 0 2.4 0.6 VDD 2.6 VDD V V clocks other inputs clocks other inputs VIL = 0 +0.6 +0.8 VDD + 0.5 VDD + 0.5 10 8 10 8 V V V V A pF pF pF
LFCO output (pin 28) LFCO output signal (peak-to-peak value) output voltage 1.4 1 2.1 - V V
1996 Nov 04
58
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA7196
MAX.
UNIT
I2C-bus, SDA and SCL (pins 3 and 4) VIL VIH I3,4 IACK VOL Tcy tr tf tSU tHD1 CL tHD2 tPD LOW level input voltage HIGH level input voltage input current output current on pin 3 output voltage at acknowledge acknowledge I3 = 3 mA -0.5 3 - 3 - - - - - - - 50 - - - - - - - - - - +1.5 VDD + 0.5 10 - 0.4 V V A mA V
Clock input timing (LLCB); see Fig.32 cycle time duty factor rise time fall time tLLCBH/tLLCB 31 40 - - 45 60 5 6 - - ns % ns ns
Data, control and CREFB input timing; see Figs 32 and 33 and note 2 set-up time hold time 11 4 ns ns
Data and control output timing; see Fig.32 and note 3 load capacitance output hold time propagation delay from negative edge of LLCB propagation delay from negative edge of LLCB (to 3-state) data, HREF and VS control CL = 15 pF data, HREF and VS; CL = 50 pF control; CL = 25 pF tPZ note 4 15 7.5 13 - - - 50 25 - 29 29 15 pF pF ns ns ns ns
Clock output timing (LLC, LLC2 and LLCB); see Fig.32 CL tLLC,tLLCB tLLC2 output load capacitance cycle time cycle time duty factor tLLCH/tLLC tLLC2H/tLLC2 tLLCBH/tLLCB 0.6 to 2.6 V 2.6 to 0.6 V at 1.5 V, 40 pF 15 31 62 40 - - - 50 40 45 90 60 pF ns ns %
tr tf tdLLC2
rise time fall time delay between LLCBout and LLC2out output hold time
- - -
- - -
5 5 8
ns ns ns
Data qualifier output timing (CREFB); see Fig.32 tHD3 tPD CL = 15 pF 3 - - - - 18 ns ns propagation delay from positive CL = 40 pF edge of LLCB
1996 Nov 04
59
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SYMBOL Horizontal PLL fHn fH/fHn nominal line frequency permissible static deviation 50 Hz system 60 Hz system 50 Hz system 60 Hz system Subcarrier PLL fSCn fSC fn f/fn nominal subcarrier frequency lock-in range PAL NTSC PAL/NTSC Crystal oscillator; see Fig.34 and note 5 nominal frequency permissible deviation fn temperature deviation from fn CRYSTAL SPECIFICATION; note 6 Tamb CL RS C1 C0 tVCLK tpL, tpH tr tf CL tHD;DAT temperature range load capacitance series resonance resistance motional capacitance parallel capacitance 0 8 - - - - - 50 70 - 80 3rd harmonic - - - 26.8 - - - 50 20 - - 400 4.433618 - 3.579545 - - - - - - - 15625 15734 - - - - PARAMETER CONDITIONS MIN. TYP.
SAA7196
MAX.
UNIT
Hz Hz % %
5.6 6.7
MHz MHz Hz
MHz ppm ppm C pF pF pF
1.1 20% - 3.5 20% - - - - - - - - -
VCLK timing; see Fig.31 and note 7 VRAM port clock cycle time LOW and HIGH times rise time fall time note 8 note 9 50 17 - - 200 - 5 6 ns ns ns ns
VRO and reference signal output timing; see Fig.31 output load capacitance VRO data hold time VRO outputs other outputs CL = 10 pF; note 10 related to LCCB (INCADR, HFL); CL = 10 pF; note 11 related to VCLK (HFL); CL = 10 pF; note 11 td VRO data delay time CL = 40 pF; note 10 related to LCCB (INCADR, HFL); CL = 25 pF; note 11 related to VCLK (HFL); CL = 25 pF; note 11 15 7.5 0 0 40 25 - - pF pF ns ns
0 - -
- - -
- 25 60
ns ns ns
-
-
60
ns
1996 Nov 04
60
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SYMBOL tD tE PARAMETER VRO disable time to 3-state VRO enable time from 3-state CONDITIONS CL = 40 pF; note 12 CL = 25 pF; note 13 CL = 40 pF; note 12 CL = 25 pF; note 13 Response times to HFL flag tHFL VOE tHFL VCLK Notes HFL rising edge to VRAM port enable HFL rising edge to VCLK burst - - - - 810 840 - - - - MIN. - - - - TYP. 40 24 40 25
SAA7196
MAX.
UNIT ns ns ns ns
ns ns
1. Levels measured with load circuits dependent on output type. Control outputs (HREF and VS excluded): 1.2 k at 3 V (TTL load) and CL = 25 pF. Data, HREF and VS outputs: 1.2 k at 3 V (TTL load) and CL = 50 pF. 2. Data input signals are CVBS7 to CVBS0, CHR7 to CHR0 (related to LLC) and YUV15 to YUV0. Control input signals are HREF, VS and DIR. 3. Data outputs are YUV15 to YUV0. Control outputs are HREF, VS, HS, HSY, HCL, SODD, SVS, SHREF, PXQ, LNQ, RTCO, RTS1 and RTS0. 4. The minimum propagation delay from 3-state to data active is 0 related to the falling edge of LLCB. 5. If the internal oscillator is not being used, the applied clock signal must be TTL-compatible. 6. Philips catalogue number 9922 520 30004. 7. CREFB-timing also valid for VCLK in transparent mode (see Fig.32). 8. Maximum tVCLK = 200 ns for test mode only. The applicable maximum cycle time depends on data format, horizontal scaling and input data rate. 9. Measured at 1.5 V level; tpL may be infinite. 10. Timings of VRO refer to the rising edge of VCLK. 11. The timing of INCADR refers to LLCB; the rising edge of HFL always refers to LLCB. During a VRAM transfer, the falling edge of HFL is generated by VCLK. Both edges of HFL refer to LLCB during horizontal increment and vertical reset cycles. 12. Asynchronous signals. Its timing refers to the 1.5 V switching point of VOE input signal (pin 53). 13. The timing refers to the 1.5 V switching point of VMUX signal (pin 46) in 32- to 16-bit multiplexing mode. Corresponding pairs of VRO outputs are together connected.
1996 Nov 04
61
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, full pagewidth
2.0 V VOE 1.5 V 0.8 V tVCLK tpH tf tpL tr 2.4 V VCLK 1.5 V 0.6 V tE not valid output VRO(n) 0.6 V tHD3(1) 2.4 V output HFL 0.6 V
MHA412
td tHD3
tD 2.4 V
td(1)
(1) Related to VCLK (HFL).
Fig.31 Data output timing (VCLK).
1996 Nov 04
62
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, full pagewidth
tLLCB tLLCBH 2.4 V
clock input LLCB
1.5 V 0.6 V tSU tf tr 2.0 V
tHD1
data input YUV, HREF, VS
not valid 0.8 V
2.0 V input CREFB 0.8 V tSU tHD1 2.0 V control input DIR not valid 0.8 V tHD2 data and control output 0.6 V tHD2 data output YUV-bus (to 3-state tLLCB tLLCBH tLLCBL 2.6 V clock output LLCB 1.5 V 0.6 V tf tr tHD2 2.4 V output CREFB 0.6 V
MHA411
tPD 2.4 V
tPZ 2.4 V
0.6 V
tHD2
tPD
Fig.32 Data input/output timing by LLCB.
1996 Nov 04
63
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, full pagewidth
tLLC tLLCH 2.6 V
clock input LLC
1.5 V 0.6 V tSU tf tr 2.0 V
tHD1
data input CVBS, CHR
not valid 0.8 V
MHA413
Fig.33 Data input timing by LLC.
handbook, full pagewidth
26.8 MHz (3rd harmonic) 10 pF X1
XTAL
(1)
1
XTAL
1
SAA7196
XTALI 2 XTALI 2
SAA7196
1 nF
10 H (20%)
10 pF
(1)
MHA414
a. Oscillator application.
b. Optional clock from external source.
(1) Value depends on crystal parameters.
Fig.34 Oscillator application circuits.
1996 Nov 04
64
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
11 PROCESSING DELAYS Table 37 Processing delays of signals PORTS CVBS/CHR to YUV YUV to VRO CVBS/CHR to VRO DELAY IN LLC/LLCB CYCLES 216 56 in YUV mode 58 in RGB mode 272 in YUV mode 274 in RGB modes -
SAA7196
REMARKS only in transparent mode only in transparent mode only in transparent mode only in transparent mode
1996 Nov 04
65
digital
handbook, full pagewidth
1996 Nov 04
15 14 13 C1 C0 C7 to C0 4.7 F 16 1 F 17 12 C2 1 F digital 15 14 19 10 16 13 20 17 12 2.2 k 21 VDDA 22 VDDD CLK 24 21 8 VDDA 22 7 26 analog 6.2 k 27 2 C6 VDDD CLK 24 CVBS4 5.6 5 28 1 68 pF 22 5.6 VDDO 3 k 3 0.1 F 25 0.1 F 0.22 F 4 5 C4 7 0.1 F 23 20 1 F 9 0.1 F 6 8 18 11 VDDO CVBS3 680 19 10 23 mH CVBS2 4.7 F CVBS1 1 F 9 1 F CVBS0 C3 4.7 F 680 18 11
GPSW1 bit (LOW = source 1)
chrominance
C
Philips Semiconductors
3
1
(J1)
S-VHS CONNECTOR
75
4
5
2
L
GND
12 APPLICATION INFORMATION
CVBS (J2)
Vi source 1 75
luminance
Vi source 2
75
TDA8709A
0.1 F 0.1 F 68 pF
33 pF
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
0.1 F
66
TDA8708A
23 6 25 CVBS5 120 4 1 k 26 CVBS6 3 27 CVBS7 5.6 2 28 1
33 pF
2.2 k
C5
0.1 F
5.6
C7
4.7 F
HSY
10
CVBS7 to CVBS0 120
analog
HCL
22
LLC
+5 V (analog supply)
+5 V (digital supply)
MHA415
Product specification
SAA7196
Fig.35 Application circuit analog-to-digital conversions.
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SAA7196
handbook, full pagewidth SDA SCL IICSA
+5 V 8 VDDD1 to VDDD7
VRO31 to VRO0
7
14, 31, 45, 61, 77, 91 and 106 5 4 3 57 to 59 62 to 74
0.1 F
VSSD
each supply has its own decoupling digital capacitor
16, 30, 47, 60, 75, 104 and 120 15, 118 and 119 (test pins)
CHR7 to CHR0
8
6 to 13
78 to 90 92 to 94
CVBS7 to CVBS0
8
17 to 24 53 54 55 56 46 116 117
SAA7196
HSY HCL RTCO RTS1 RTS0 +5 V CGCE BTST GPSW1 GPSW2 X1: Philips 9922 520 30004 1 X1 26.8 MHz 2 10 pF 10 H 10 pF 1 nF RESN LLC CREF 36 40 38 29 VSSA 95 25 26 44 34 35 37 43 33 32
VOE HFL INCADR VLCK VMUX VS HS
96 to 103 107 to 114
16
115 HREF
digital
76, 39 41 42 28 48 49 50 51 52 105 27 LLCB LLC2 VDDA CREFB LFCO SVS PXQ i.c. 2.2 H 0.1 F
DIR
JP2
47 k VDDD
SODD SHREF LNQ 10 F VDDA analog
8
8
1,3,5, 7,9,11, 13,15
2,4,6, 8,10,12, 14,16
EXPANSION CONNECTOR 17 19 21 23 25 JP1 18 20 22 24 26
MHA416
Fig.36 Application of SAA7196.
1996 Nov 04
67
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
12.1 Programming example
SAA7196
Coefficients to set operation for application circuits Figs 35 and 36. Slave address byte is 40H at pin 5 connected to VSSD (or 42H at pin 5 connected to VDDD). Table 38 Programming examples SUBADDRESS 00 01 02 03 04 05 06 BITS IDEL7 to IDEL0 HSYB7 to HSYB0 HSYS7 to HSYS0 HCLB7 to HCLB0 HCLS7 to HCLS0 HPHI7 to HPHI0 FUNCTION increment delay H-sync beginning for 50 Hz H-sync stop for 50 Hz H-clamp beginning for 50 Hz H-clamp stop for 50 Hz HS pulse position for 50 Hz 4C 30 00 E8 B6 F4 01(1) VALUE (HEX)
BYPS, PREF, BPSS1 and luminance bandwidth control BPSS0, CORI1 and CORI0, APER1 and APER0 HUEC7 to HUEC0 CKTQ4 to CKTQ0 CKTS4 to CKTS0 PLSE7 to PLSE0 SESE7 to SESE0 COLO, LFIS1 and LFIS0 VTRC, RTSE, HRMV, SSTB, SECS HPLL, OECL, OEHV, OEYC, CHRS, GPSW2 and GPSW1 AUFD, FSEL, SXCR, SCEN, YDEL2 to YDEL0 HRFS, VNOI1 and VNOI0 CHCV7 to CHCV0 SATN6 to SATN0 CONT6 to CONT0 HS6B7 to HS6B0 HS6S7 to HS6S0 HC6B7 to HC6B0 HC6S7 to HC6S0 HP6I7 to HP6I0 BRIG7 to BRIG0 reserved RTB, OF1 and OF0, VPE, LW1 and LW0, FS1 and FS0 XD7 to XD0 XS7 to XS0 hue control (0 degree) colour-killer threshold QUAM colour-killer threshold SECAM PAL-switch sensitivity SECAM switch sensitivity chrominance gain control settings standard/mode control I/O and clock controls
07 08 09 0A 0B 0C 0D 0E
00 F8 F8 40 40 00 04(2)(3); 05(4)(3) 38, 3B(5)
0F 10 11 12 13 14 15 16 17 18 19 1A to 1F 20
miscellaneous controls #1 miscellaneous controls #2 chrominance gain nominal value chrominance saturation control value luminance contrast control value H-sync beginning for 60 Hz H-sync stop for 60 Hz H-clamp beginning for 60 Hz H-clamp stop for 60 Hz HS pulse position for 60 Hz luminance brightness control value set to zero data formats and field sequence processing LSBs output pixel/line LSBs input pixel/line 68
90 00 2C(6); 59(7) 40 40 34 0A F4 CE F4 80 00 10(8)
21 22 1996 Nov 04
80(9); FF(10) 80(9); FF(10)
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
SUBADDRESS 23 24 BITS XO7 to XO0 HF2 to HF0, XO8, XS8 and XS9, XD8 and XD9 YD7 to YD0 YS7 to YS0 YO7 to YO0 AFS, VP1 and VP0, YO8, YS8 and YS9, YD8 and YD9 VS7 to VS0 VC7 to VC0 VS8,VC8, POE VL7 to VL0 VU7 to VU0 UL7 to UL0 UU7 to UU0 VOF, AFG FUNCTION LSBs for horizontal window start position horizontal filter select and MSBs of subaddresses 21, 22, 32 LSBs output lines/field LSBs input lines/field LSBs vertical window start position MSBs of subaddresses 25, 26, 27
SAA7196
VALUE (HEX) 03(9); 00(10) 85(9); 8F(10)
25 26 27 28
90(9); FF(10) 90(9); FF(10) 03(9); 00(10) 00(9); 0F(10)
29 2A 2B 2C 2D 2E 2F 30 Notes
LSBs vertical bypass start position LSBs vertical bypass lines/field MSBs of subaddresses 29, 2A and odd/even polarity switch chroma key: lower limit V (R-Y) chroma key: upper limit V (R-Y) chroma key: lower limit U (B-Y) chroma key: upper limit U (B-Y) VRAM port MUX enable, adaptively
00(11) 00(11) 00(11) 00 FF(12) 00 00 80(13)
1. Dependent on application (Figs 35 and 36). 2. For QUAM standards. 3. HPLL is in TV-mode, value for VCR-mode is 84H (85H for SECAM VCR-mode). 4. For SECAM. 5. For Y/C-mode. 6. Nominal value for UV-CCIR-level with NTSC source. 7. Nominal value for UV-CCIR-level with PAL source. 8. ROM-table is active, scaler processes both fields for interlaced display; VRAM port enabled; long word position = 0; 16-bit 4 : 2 : 2 YUV output format selected. 9. Scaler processes a segment of (384 pixels x 144 lines) with defaults XO and YO set to the first valid pixel/line and line/field (for decoder as input source) with scaler factors of 1 : 1; horizontal and vertical filters are bypassed, filter select adaptability is disabled. 10. If no scaling and panning is wanted, the parameters XD, XS, YD and YS should be set to maximum (3FFH) and the parameters XO and YO should be set to minimum (000H). In this case, the HREF and VS signals define the processing window of the scaler. 11. No vertical bypass region is defined. 12. Chrominance keyer is disabled (VL = 0, VU = -1). 13. 32-bit to 16 VRAM port MUX, adaptive scale and Y-limiter are disabled; pixel and line qualifier polarity for transparent mode are set to zero (active); data burst transfer for the 32-bit long word formats is set.
1996 Nov 04
69
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
13 PACKAGE OUTLINE QFP120: plastic quad flat package; 120 leads (lead length 1.95 mm); body 28 x 28 x 3.4 mm; high stand-off height
SAA7196
SOT349-1
c
y
X
A 90 91 61 60 ZE
e E HE A A2 A1
Q (A 3) Lp L detail X
wM bp pin 1 index 120 1 bp D HD wM 30 ZD B vM B vM A 31
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT349-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 3.95 A1 0.40 0.25 A2 3.70 3.15 A3 0.25 bp 0.45 0.30 c 0.23 0.13 D (1) 28.1 27.9 E (1) 28.1 27.9 e 0.8 HD 32.2 31.6 HE 32.2 31.6 L 1.95 Lp 1.1 0.7 Q 1.70 1.55 v 0.3 w 0.2 y 0.1 Z D (1) Z E (1) 2.6 2.2 2.6 2.2 8 0o
o
ISSUE DATE 93-08-25 95-02-04
1996 Nov 04
70
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
14 SOLDERING 14.1 Introduction
SAA7196
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Repairing soldered joints
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 14.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 14.3 Wave soldering
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
1996 Nov 04
71
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
15 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7196
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 17 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Nov 04
72
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
NOTES
SAA7196
1996 Nov 04
73
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
NOTES
SAA7196
1996 Nov 04
74
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock generator circuit (DESCPro)
NOTES
SAA7196
1996 Nov 04
75
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 247 9145, Fax. +7 095 247 9144 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
657021/1200/01/pp76
Date of release: 1996 Nov 04
Document order number:
9397 750 01459

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